[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.

Filed under: FEL, IP, asic, emacs, feature, fedora, xcircuit

[FEL]: Recent updates are minor enhancements

The following packages have pushed (timeframe: from last week till today) to the repositories to ensure stability and extra device support.

xcircuit 3.6.164 :

• Fixed crash while creating a symbol from schematic with no component name.

ngspice rework 20 :

I’ve blogged about ngspice rework 20 fedora release 1 here. Yesterday ngspice rework 20 fedora release 3 was pushed to repositories, with improved interoperability with xcircuit. New blog post will detail that feaure. Our fedora ngspice was pulling this patch for quite some time now. Upstream (Holger Volt) improved and applied the patch to the CVS branch. While waiting for the next release perhaps ngspice rework 21, fedora users can benefit it with ngspice-20-3.

gnusim8085 1.3.5-6:

• Bug RHBZ 542945 fixed :  crash on click on the about menu

toped 0.9.51-1:

Krustev Svilen finished the workaround for the reported start-up crash with Mesa DRI on Intel(R) 945GM. The issue is described here.

Toped now have a command line option (-ogl_safe) which will force the renderer to use only basic openGL functionality. This will allow the users run the program on untested graphical platforms.

The initial diagnostic of the graphic platform is also updated to be more conservative. This will be the case until he has more clear answers from the 945GM DRI developers.

pcb 0.20091103-2

Fedora/EPEL-5’s pcb package was recompiled with dbus support enabled. Thus this allows xgsch2pcb to communicate with pcb and gschem. RFE RHBZ 541879.

vrq 1.0.67

ShakthiKannan has pushed this bug release to the repositories. Please read the ChangeLog for more details carried out by upstream.

$ rpm -qd vrq | grep ChangeLog

(new package) : emacs-irsim-mode

Arun SAG now maintains irsim-mode. It should hit mirrors in one or two days. It provides two features : indentation and syntax highlight on emacs. This will be the delight for those users who conduct event driven simulation and stuck-at fault simulation with irsim from sim netlists.

Filed under: FEL, eda, feature, fedora

[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

• Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
• Piecewise linear(PWL) functionality for B sources.
• Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
• New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

…

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

…

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Filed under: FEL, asic, eda, feature, fedora, ngspice

[FEL] Tip: Verilog lint with Emacs

Verilator has verilog lint capabilities aside its main robust functionality : Verilog code to C++/SystemC conversion.

# yum install verilator

$ verilator –lint-only mydesign.v

Coupled with verilog-mode, it can really boost productivity for the experienced designer just by adding the following to the .emacs file.

(setq verilog-linter “verilator –lint-only”)

Currently we are making a request to upstream so that vhdl-mode and verilog-mode bundled with emacs can be updated. Possibly this should be also be enabled by default.

Filed under: FEL, emacs, verilog

[FEL]: Circuit simulation improved

Paolo Nenzi, Dietmar, Holger Vogt and Robert Larice have contributed to the enhanced stability with the new ngspice rework 20 release. ngspice rework 20 has already been pushed to fedora stable repositories with the following enhancements:

• Model names can start with a number like 1N4001
• .global command reinstated (was disabled)
• Error messages now display line number of input deck
• [feature]: .measure with tran, ac and dc (not yet complete, e.g DERIV is missing)
• [feature]: sysinfo command added
• [device]: Updated bsim4 model to BSIM 4.6.5
• [device]: Added PWL functionality for B sources

Currently Holger Vogt is kindly looking after my variable instantiation feature request for the .measure command. Hopefully after some testing, we can push another release to the stable repositories so that fedora users can largely benefit from it as soon as possible. I will write another blog post to demonstrate how to use this small but valuable feature.

Al Davis, who is working behind gnucap, is considering system-c plugins for gnucap, probably without their run-time package. Gnucap provides a lot of the needed run time support already. It might be all that is needed is to map the interface. That said, we will have to update fedora gnucap package to the latest development snapshots with the help of Rakesh Pandit (current fedora gnucap maintainer). This will give fedora users the chance to use gnucap plugins and latest enhancements over the current 0.35 stable repositories. This deserves another blog post .

Arun Sag is working on pushing some emacs mode to the fedora repositories. Among these emacs modes, there are irsim-mode and and spice-mode (see the above screenshot). Many users will enjoy the look-and-feel on their fedora emacs. I’m taking the opportunity to remind Fedora users that irsim has stuck-at fault simulation and power estimation capabilities.

Filed under: FEL, eda, emacs, fedora, gnucap, ngspice

[FEL]: Icarus Verilog bug statistics

Cary R. published some statistics about the amount of time spent in bug fixing for the most widely used opensource verilog simulator, Icarus Verilog. I’m quoting:

Excluding the VHDL work, so far in 2009 we have had 25 invalid bug reports, 87 valid bug reports. Eight of these are still open. It took on average 12 days to fix a bug and the open bugs have been open for an average of 177 days. That attached plot shows the details much better.

Icarus Verilog development team is heading towards the release of 0.9.2, which will be realeased pretty soon. If you are encountering some other bugs on 0.9.1 (the current fedora iverilog version), please do file bug reports so that they can be fixed for the 0.9.2 release.

In the past, I’ve described how to use iverilog for post-synthesis simulation and how to access documentation quickly to ensure interoperability and other verilog variants. If you are encountering issues while dealing with FPGA and iverilog, please feel free to share it with us.

Filed under: eda, iverilog

Don’t say No cuesheet support to Trance Music !

Unlike many people, I love Trance music and not only I like it but it’s the only type of music I can listen anywhere and anytime, while sleeping, while working 10 or more hours straight on complex VHDL/Verilog designs, … and still be productive.

However Amarok (the player I advised people to use at that time) developers dropped Cuesheet support since they move towards the 2.0 branch. Some of the other trance addicts have already filed RFE, but now nearly two years already still the 2.* series is pretty useless to be proud of.

• no cuesheet support.
• no ipod support.
• cover fetching feature broken.
• text on widgets overlap on the gui like spaghetti.

I have some complex Verilog designs to complete and yet to interface with analog. These lack of features on media players are not good for my productivity and neither can I vote the “tunes of the week” in the Trance community.

Since I have some friends who are DJs, I receive their two hours livesets straight from the studio along with the cuesheet (nowadays I am using the IPOD as a USB stick to such transfer).

I had to dual both Centos-5 and Fedora-12 so that I can still use Amarok 1.4 for my work. But soon the lack of software compatibilities between CentOS-5 and Fedora-12, I decided dual boot is not making me productive.

For about two months now, I’ve been experimenting many music players, both opensource and proprietary. The one which matches most of my needs was Rhythmbox. The latter was. in the past, among the first software to yum remove after a clean install. I’m impressed with Rhythmbox autosupport for cover transfer while transferring music from Rhythmbox to my IPOD nano. The GUI of Rhythmbox is not WOW, but at least it’s far more stable than that of Amarok 2 spagettis.

I spent days looking for cuesheet support or related plugins online. For some reason people out there use cuesheet to split last mp3s only. But why ? In the Trance Community a DJ releases a set, every week one will hear a new remix of the same music. Splitting also refers to the zero offset issues most media players suffer and one must manually rename all the remixes by hand. Doesn’t it defeat the purpose? I’ve even decided to port that on Rhythmbox. But python, oh dear after one week, I decided that it was too software for me to play with. Hence the quickest way for me to get cuesheet support and start playing with Verilog and also learn the new features of the VHDL IEEE standard 1076-2008, was to write a simple Tk script coupled with a basic python script to interface with DBUS.

For the time being, these scripts do the basic stuffs.

• Read the cuesheet file of the mp3 being played on rhythmbox
• List all the tunes on a tktable
• Allow double clicks to switch tunes within the same mp3
• On track change, restart Tcl/Tk. This could be automated if I find time. But since each mp3 plays for about 2hours non-stop, restarting the script doesn’t affect much.

$ wish cuesheet.tcl

If one likes amarok, I believe, tuning the python script one can get this cuesheet support on amarok too.

Filed under: Uncategorized

Report from France: FEL at JM2L – Nov 27-28 2009

Fedora Electronic Lab and Upstream developers were represented by Laurent Charpentier, whom I sincerely thank for his presentation last friday and booth attendance. Photos in this blog post are from Animatrix30.

Report of the JM2L 2009 event in Sophia-Antipolis, France – Nov 27-28 2009

by Laurent Charpentier

The JM2L event (Journée Méditerranéennes du Logiciel Libre), dedicated to opensource software, took place at the University of Nice-Sophia, France.

Sophia-Antipolis, one of Europe’s largest technology parks, is home to hundreds of high tech companies, primarily in information technology, telecommunications and biotechnology fields.

Exhibitors came on Friday morning to set-up the booths. We had about 15 booths including one for Fedora Project (and Fedora Electronic Lab sub-project).

Booth setup:

Doors opened on Friday afternoon with a good mix of visitors coming from the University (students, teachers) and professionals from the Sophia technology park.

The event had 30 conferences, 6 technical workshops. Several rooms were also set-up for Linux installation (“install party”) and video games (“LAN party”).

At the Fedora booth I presented Fedora 12 and Fedora Electronic Lab 12, the latest version of these distributions. Most of the Fedora visitors at the booth came to know about FEL. HDL design, simulation and PCB design were among the fields of interest. I gave some demos of Kicad (PCB) and KtechLab (simulation). I also had questions about Fedora distribution: what is Fedora? what is Fedora compared to Ubuntu? I also had one installation to perform on a (old) Samsung X30 notebook, but the F12/F11/F10 live CDs failed to run (X server failed to run). It worked however on Ubuntu the previously installed OS.

On Friday I gave a presentation of Fedora and Fedora Electronic Lab (presentation is available on FEL’s website, pictures on flickr using “jm2l09″ and “fedora” tags). I had about 20 persons attending the presentation, some of them were Electrical Engineers from local semiconductor companies (Infineon, Texas-Instruments, ST-Ericsson, …). The attendants were very pleased to know about the FEL initiative: it is now easier to find opensource tools that are ready to use.

Some of the questions were: why some projects are not included in FEL (systemC, Scilab, openaccess, …)? It is due to licensing restrictions. Does FEL work closely with FPGA vendors to use/integrate opensource tools into their design flow?

Overall, JM2L was a good event promoting opensource software and strengthening the opensource community. JM2L had a lot of conferences including technical sessions and workshops to present opensource software to a broad range of visitors.

Laurent Charpentier

Filed under: FEL, events

Hello Planet Qi Hardware

First, I would like to thank Wolfgang Spraul for adding my blog to the Planet Qi Hardware: Freedom Redefined.

So, hello Planet Qi Hardware

I’m Chitlesh Goorah (a digital IC design engineer) and contribute to the opensource EDA community through the Fedora Project during my spare time. Together with a couple of contributors and upstream developers, we hope to provide opensource Hardware communities with opensource EDA software that satisfy real life electronic design flows through Fedora Electronic Lab.

While my passion is ASIC design, we try our best to provide “design flow” solutions and interoperability rather than point software. That said, I believe this blog post about OpenMoko will give you an idea where FEL stands.

Please feel free to contact me if you feel we can improve the bridge between opensource Hardware communities and opensource EDA software communities.

Filed under: blog

[FEL]: Power Estimation at transistor Level

One of the least advertised features of IRSIM is its ability to quickly estimate power of large VLSI circuits from gate level netlists (.sim).

To install IRSIM on Fedora (default on Fedora Electronic Lab):

# yum install irsim

This estimation is based on the

• ‘three-level quantization scheme’, where the voltage can assume 3 values (GND, VDD/2 and VDD). It is fairly more accurate than the ‘two-level rail-to-rail model’.
• measurement of glitching power.
• estimates reasonably close to those that can be derived by measuring currents with a SPICE simulator with an error of less than 20% and a speed up of about 500 times.
• incremental power measurement.

Filed under: asic, opencircuitdesign