Icarus Verilog (iverilog) is a verilog compiler and simulator.
Icarus Verilog generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364-2005 standard.
The related documentation of iverilog and examples can be found via
$ man vvp $ man iverilog $ man iverilog-vpi $ rpm -qld iverilog
Installation and Version
To install Icarus Verilog (including the PLI headers):
# yum install iverilog
FEL ships the stable 0.9.5 version. Learn more about the QA test carried out against iverilog.
All the mentioned documentation below can be found via
$ rpm -qld iverilog | grep DOC
- Supports attributes to control synthesis – More details : attributes.txt
- Supports some extensions of verilog variant: !SystemVerilog – More details : extensions.txt
- FPGA code generator – More details : fpga.txt
- Compatibility with the Cadence PLI module – More details : cadpli.txt
- Accessible Standard Verilog-A Mathematical Constants. – More details : va_math.txt
- VPI interface supporting trace – Environment variable : VPI_TRAC – More details : vpi.txt
SDF Back Annotation (in devel snapshot)
Fri, Apr 2, 2010 at 7:26 PM
Icarus still does not support interconnect delays or timing checks (which can created delayed signals), but the SDF back annotation for what is supported appears to work correctly except for pr2070488 which will be fixed once the expression rework is completed.
If you have a $setuphold or $recrem that is creating a delayed signal the compiler will warn you that these nets will not be driven. Your standard cell library may have an option/define that allows you to use the non-delayed version of these timing checks.
Only development (v0.10.devel) has all the patches needed to make this work.
Icarus versus IEEE Std. 1364-2005
A list of known Icarus deficiencies relative to 1364-2005 (by Cary R.)
- Constant user functions are not supported, but $clog2() and the other math functions are available.
- Timing checks are not supported, but they should be fully ignored.
- Specify block pulse filtering control is not supported.
- Net delays are not supported. Because of this there is no infrastructure to support interconnect delays from a SDF file.
- Trireg nets are not supported.
- Only one-dimensional arrays are supported.
- The $fmonitor family of system tasks are not supported.
- The stochastic analysis and PLA modeling tasks are not supported.
- Design configuration is not supported.
- The `pragma compiler directive is not supported.
- Force/procedure continuous assign from a non-constant expression is not supported except for a simple variable. This can be emulated by creating a continuous assignment to a dummy variable for the expression and then use that variable in the force/assign.
- $monitor/$strobe of a complex expression may have problems. Only a simple variable, bit, part or array select is fully supported. Anything else will get the value when the system task/function was called. Use a continuous assign to a dummy variable and then $monitor/$strobe that variable to work around this limitation.
- A uwire is treated just like a wire. It does not check for only one driver.