Fedora Electronic Lab 8 – Stable release

Last Thursday, 8th November 2007, the very first Fedora Electronic Lab LiveCD was released officially. This LiveCD is based on Fedora 8 KDE along with almost all electronic design tools.

Fedora’s Electronic Laboratory provides a complete electronic laboratory setup with reliable open source design tools in order to meet one’s requirements to keep one in pace with current technological race. Project management tools such as spreadsheet, gantt diagram, mindmapping tools…. are also included. This Electronic Laboratory can either be deployed by:

• yum or
• a Fedora Electronic Lab LiveCD

Download Fedora Electronic Lab LiveCD NOW via torrent

Read the abstract, the flyer or its website for more details.

For Fedora 8′s release, “Fedora Electronic Lab” targets mainly the Micro-Nano Electronic Engineering field. It introduces:

• tools for Application-Specific Integrated Circuit (ASIC) Design Flow process to the Fedora Collection.
• extra open source standard cell libraries supporting a feature size of 0.13µm. (more than 300 MB)
• extracted spice decks which can be simulated with gnucap/ngspice or any spice simulators.
• interoperability between various packages in order to achieve different design flows.

Filed under: electronics, fedora, Free Electronic Lab, livecd, VLSI

FEL – Fabless Semiconductor business model

You don’t have financial strength to invest in building your own foundry in order to fabricate your chips?
You are opting for a fabless business model for trial (focusing on design and outsourcing the actual manufacturing) ?

The Fedora Project proposes a free fabless semiconductor business model for your needs, thus allowing you to stay focused on cutting-edge design, and not invest in manufacturing.

With the “Fedora Electronic Lab” along with its RPM package management, any electronic engineer can deploy his/her VLSI simulation environment quickly and easily. You will have tools for RTL simulation, place & route, timing closure up to digital physical design. In addition, 7 opensource technology libraries are available with a feature size up to 0.13µm.
You are free to decide whether your design process will be either top-secret or open to the world. However the simulation tools will be free. Processes can be modified and created graphically (if desired).

Extensive work was done to provide enough interfaces useful for your automated configuration scripts (e.g Makefiles).

On the Fedora Electronic Lab livecd, you will benefit from the KDE desktop environment in terms of

Project implementation tracking capabilities

Visibility to assigned tasks, resources and issues

The Fedora Repositories entail a wide range of applications with graphical means to manage all aspects of data flow throughout an enterprise in a highly efficient manner.

Filed under: fedora, Free Electronic Lab, kde, VLSI

EDA: standard cells for chip design

A standard cell is group of transistor and interconnect structures, which provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). All CAD tools for chip design (whether proprietary or open source) require standard cell libraries. These standard cell libraries contain primitive cells required for digital design.

A fedora user will have some standard cell libraries from

the alliance package

the pharosc package

# yum install pharosc\*

Pharosc provides five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

The libraries have been characterized in a generic 0.13µm technology, compatible with most foundry rules. Pharosc is the result of a book that Graham Petley is writing, The Art of Standard Cell Library Design.

Among the standard cells from pharosc there are many scripts to provide interoperability between magic, alliance and xcircuit as well as scripts to allow one to update actual cells or create his/her own cells (pharosc-devel). There are more than 500 spice decks which can be simulated with either gnucap or ngspice.

Each single component in any standard cell library comes with a well documentation html manual.
The latter entails schematics, layouts and several parameters for spice simulation. The transistor schematics for the libraries have been drawn with Xcircuit, which uses Postscript as its native file format.

Pharosc entails Alliance’s sxlib which has been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly.

Filed under: asic, fedora, semiconductor, VLSI

EDA: Physical Layout is done, so what’s next? (PART_1)

Whether you are a student, lecturer, VLSI amateurs or professionals, there is no way that you can prevent yourself from using proprietary softwares such from Cadence, Altera…

In the semiconductor world, students/trainees are taught under proprietary softwares so as they could be attractive for companies recruiting them. Similarly, students studying accounting or economics are taught under Microsoft Office instead of OpenOffice for the same reason. Sadly, this is the truth.

However proprietary softwares for the semiconductor world are so expensive that one can’t afford for personal use (much more expensive than Vista, to give you an idea). Opensource might be an alternative. Thereby, the question of exchanging one’s work between applications raises. I’ll talk about layout editors for now. Each layout editor has its own file format. It would be useless to design a layout if one can’t do much with its design. By useless, I mean waste of time and money. Mature EDA CADs like magic and alliance (soon on fedora) do provide exports to the GDS II stream format (GDSII) or Caltech Intermediate Form (CIF) provided the proper technology has been fed.

Now, students can design at home with magic, alliance (soon on fedora) or toped on their Fedora. Then demonstrate their achievement on Cadence’s Virtuoso at school, for example. But on Fedora, one isn’t only restricted to Layout editing, but can also:

extract spice netlists, simulate the latter with ngspice or gnucap (we will soon see gspiceui and gwave into the fedora collection in the next 2 weeks)

do Switch-level simulation with irsim

do VHDL simulations with either ghdl and freehdl along with gtkwave.

do large analog or mixed-signal circuits simulations

do schematics with xcircuit, xsch or gschem

design pcb with the couple geda suite and pcb. or with kicad and view under gerbv

do LVS with alliance (soon on fedora)- However for now netgen is giving segmentation faults.

..

(not semiconductor related: gpasm, gpsim, piklab, ktechlab and pikloops useful for pic programming)

All these to say, Fedora has included and will continue to include big opensource names in terms of electronic simulations. By F8′s release, alliance, gspiceui and gwave will be available on the fedora collection, making electronic simulations one of F8′s features. If you feel something is missing in Fedora’s Electronic Simulation Kit or simply give feedbacks, please drop me a mail (chitlesh [AT] fedoraproject DOT org). I’ll be delighted to make Fedora provide an Electronic Simulation Kit with which one can do _real_ job!

In Physical Layout is done, so what’s next? (PART_2), I’ll demonstrate an example of invertor using the TSMC 0.25µm SCN5M_DEEP technology.

Filed under: alliance, electronics, magic, VLSI