FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP

The picture shows the respective eclipse-plugins, which will enhance :

• frontend design
• autogeneration of documentation and maintenance of professional datasheets
• Perl/Tcl scripting (Perl modules which featured as from FEL10)
• version controlled

experience for Fedora users.

Think Methodology and not random packaging.

This is sentence that many people have heard from me. Feeding design methodologies is one of the reasons why Fedora Electronic Lab  is so attractive to many small companies.

Development behind FEL 12 focusses on adding value to the frontend design. Eclipse, being an industry standard IDE, is FEL’s main IDE for digital/embedded hardware design.

In the following blog posts, I will cover these features in depth, meanwhile you can try those plugins with yum on your Fedora 11. Only eclipse-eclox and eclipse-texlipse are not yet part of the Fedora collection. They are being reviewed #506429 and #506431 respectively.

Filed under: eclipse, eda, fedora, fpga, Free Electronic Lab, IP, perl, tcl, verilog, vhdl

JTAG Controller

Today, I spent some time to complete my JTAG Controller VHDL design. I started it a few days before Fedora Electronic Lab 11 release.

I was also awaiting the day when someone will talk about a possible merger of Cadence and Magma. Well that news was among my RSS feeds. John Cooley’s email about Apache-DA’s Techguri blogsite got my attention though. On the other hand, Cadence and Synopsys have paid bloggers.

Filed under: eda, vhdl, eda, jtag

FEL: Tidy your VHDL files with a simple Perl script

One of the problems digital designers encounter while working with VHDL is that every designer seems to have his/her coding style. Though many companies enforce some coding styles, some files still entail ad-hoc tabs and spacings.

Fedora and EPEL-5 repositories include perl-Hardware-Vhdl-Tidy which helps digital designers from pulling their hairs off while working in a complex ASIC/FPGA design.

To install perl-Hardware-Vhdl-Tidy on Fedora :
# yum install perl-Hardware-Vhdl-Tidy

Below is a perl script that you can copy-paste in a file “tidyvhdl.pl” and parse your vhdl file as an argument.

#!/usr/bin/perl
use strict;
use warnings;

use IO::File;

use Hardware::Vhdl::Tidy qw/ tidy_vhdl_file /;

my $infile   = $ARGV[0];
my $tempfile = IO::File->new_tmpfile;

# -----------------------------------------------------
# Tidying original and dumping output into a temp file
# -----------------------------------------------------
tidy_vhdl_file( {
    source               => $infile,
    destination          => $tempfile,

    indent_spaces        => 4,
    tab_spaces           => 4,
    cont_spaces          => 0,
    starting_indentation => 0,
    indent_preprocessor  => 0,
    preprocessor_prefix  => '#',
} );
# -----------------------------------------------------

Filed under: perl, vhdl