[FEL]: New stable release of perl-Verilog-Perl

Verilog-Perl 3.314(15926 – the PI version!) is released and pushed to Fedora and EPEL6 testing repositories.

Verilog::Language 3.314 2012/02/27 ChangeLog
- vhier –forest and –instance. [by John Busco]
- Fix expansion of back-slashed escaped macros, bug441. [Alberto Del Rio]
- Fix -F relative filename parsing, bug444. [Jeremy Bennett]
- Fix c style var array declarations. [by Jack Cummings]
- Fix –debug parsing after -f files, bug442. [Jeremy Bennett]
- Fix hang on recursive substitution `defines, bug443. [Alex Solomatnikov]

Filed under: Free Electronic Lab, perl, verilog

FEL: Bugfix release of SystemPerl

SystemPerl 1.336 2010/11/03

• Fix support for Verilog-Perl 3.305; removing defines, bug300.

It will soon be among your updates. Special credits go to Veripool.

 

Filed under: Free Electronic Lab, perl, systemc, verilog

FEL: Bugfix release of Verilog-Perl 3.304

Verilog::Language 3.304 released on 2010/10/25 fixes wrong filename on include file errors, bug289, by Brad Parker. This bug fix will soon be available among your FEL updates.

Filed under: Free Electronic Lab, perl, verilog

FEL: Bugfix release of Verilog-Perl 3.303

Minor enhancements :

• Add vrename –changelang option, to upgrade keywords. [Dan Moore]
• Add vrename –language option. [Dan Moore]
• Add Verilog::Language::language_maximum and language_keywords.
• Fix escaped identifiers that are keywords, bug282. [Dan Moore]
• Fix preprocessor “ of base define, bug283.  [Usha Priyadharshini]

It will soon be among your updates. Special credits go to Veripool. For those in a hurry:

# yum install perl-Verilog-Perl --enablerepo=updates-testing

Filed under: perl, verilog

FEL: Bug fix release of Icarus Verilog 0.9.3

The Icarus Verilog developers are pleased to announce the next stable release in the 0.9 series, version 0.9.3. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions.
Icarus Verilog 0.9.3 improves language coverage over the previous stable release, but is primarily a bug fix release. Therefore, we recommend people using the 0.9.2 release upgrade to 0.9.3 as soon as possible. Version 0.9.3 is the recommended version for all new users.

More details, including known limitations, deviations from IEEE Std 1364-2005, can be found in the Release Notes located here.

Icarus Verilog 0.9.3 will be available soon on update-testing repositories:

# yum install iverilog --enablerepo=updates-testing

Filed under: iverilog, verilog

FEL: Bugfix release of Perl-Verilog 3.302

Verilog::Language 3.302 was released shortly after 3.300 to fix a few bugs, namely

• Increase define recursions before error.  [Paul Liu]
• Fix documentation on verilog_text and link, bug278. [Mike Z]
• Use Digest::SHA instead of SHA1, bug189.  [Ahmed El-Mahmoudy]
• Fix false test failure if Math::BigInt not installed.

It will soon be among your updates. Special credits go to Veripool.

Filed under: perl, verilog

[FEL]: Verilog-Perl 3.300 *Beta1*

We’d like your help to test the next release of Verilog-Perl.  A beta release of the next Verilog-Perl release is available on Rawhide:

$ yum install perl-Verilog-Perl --enablerepo=rawhide

This version adds support for 99% of the SystemVerilog 2009 standard, and also fixes a number of preprocessor bugs and other issues.  These changes were massive enough that it may have broken some existing code, however the user interface is identical to the 3.200 series, so your existing scripts should work.

Filed under: perl, verilog

[FEL] Tip: Verilog lint with Emacs

Verilator has verilog lint capabilities aside its main robust functionality : Verilog code to C++/SystemC conversion.

# yum install verilator

$ verilator –lint-only mydesign.v

Coupled with verilog-mode, it can really boost productivity for the experienced designer just by adding the following to the .emacs file.

(setq verilog-linter “verilator –lint-only”)

Currently we are making a request to upstream so that vhdl-mode and verilog-mode bundled with emacs can be updated. Possibly this should be also be enabled by default.

Filed under: emacs, Free Electronic Lab, verilog

FEL: Perl-Verilog bugfix release 3.212

A bugfix release of perl-Verilog was just pushed to Fedora stable repositories which fixes the following

• syntax errors when using vhier/Netlist with –language 1364-2001.
• dotted expressions returning “..”, bug98. [Saul Cuellar]
• Getopt::file_path to expand environment variables in filenames.

Tips of the user

The perl-Verilog package includes several examples and manuals. To learn more about those examples and manuals, please consult:

$ rpm -qd perl-Verilog

Filed under: Free Electronic Lab, perl, verilog

FEL: Icarus Verilog: more than simulator

This blog post highlights the VPI bug fix and some hidden features of iverilog which most verilog users are not aware. Fedora proposes Icarus Verilog for verilog simulation. The related documentation of iverilog and examples can be found via

• man vvp
• man iverilog
• man iverilog-vpi
• and rpm -qld iverilog

To install Icarus Verilog on Fedora:

# yum install iverilog

Icarus Verilog is available on the Fedora Electronic Lab livedvd.

Keys features of Icarus Verilog

All the mentioned documentation below can be found via

$ rpm -qld iverilog | grep DOC

Use any text editor of your choice to open them.

• Supports attributes to control synthesis

More details : attributes.txt

• Supports some extensions of verilog variant: SystemVerilog

More details : extensions.txt

• FPGA code generator

More details : fpga.txt

• Compatibility with the Cadence PLI module

More details : cadpli.txt

• Accessible Standard Verilog-A Mathematical Constants.

More details : va_math.txt

• VPI interface supporting trace

Environment variable : VPI_TRAC

More details : vpi.txt

# yum install iverilog-devel

Filed under: feature, fedora, Free Electronic Lab, verilog