Free Electronic Lab

Opensource EDA software development, some thoughts about the EDA/Semiconductor industry and Mixed-signal integrated circuit design

FEL: Bugfix release of Verilator 3.805

Verilator 3.805 2010/11/02

  • Add warning when directory contains spaces, msg378. [Salman Sheikh]
  • Fix wrong filename on include file errors, bug289. [Brad Parker]
  • Fix segfault on SystemVerilog “output wire foo=0″, bug291. [Joshua Wise]
  • Fix DPI export name not found, msg369. [Terry Chen]

It will soon be among your updates. Special credits go to Veripool.

Filed under: Free Electronic Lab, perl, verilator

FEL: Bugfix release of Verilator 3.804

  • Support tracing/coverage of underscore signals, bug280. [by Jason McMullan]
  • Fix preprocessor “ of existing base define, bug283. [Usha Priyadharshini]
  • Increase define recursions before error. [Paul Liu]
  • On core dump, print debug suggestions.

It will soon be among your updates. Special credits go to Veripool.

Filed under: verilator

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Chitlesh Goorah
Digital IC design engineer
Neuchâtel, Switzerland

This blog is featured on Sean Murphy's EDA blogger list.

June 2013
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