Cleaning dead leaves

Before

foreach attr $the_attributes {
  if { [ set value [ get_attribute $o $attr ] ] != “” && $attr == “ref_name” } {
    if { $verbose } { 
       echo [ format "%-30s %30s" $name $value ] 
    }
    lappend _ref_name $value
  }
}

After

set value [ get_attribute $o "ref_name" ]
if { $value != “” } {
   if { $verbose } { 
      echo [ format "%-30s %30s" $name $value ] 
   }
   lappend _ref_name $value
}

Filed under: tcl

FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP

The picture shows the respective eclipse-plugins, which will enhance :

• frontend design
• autogeneration of documentation and maintenance of professional datasheets
• Perl/Tcl scripting (Perl modules which featured as from FEL10)
• version controlled

experience for Fedora users.

Think Methodology and not random packaging.

This is sentence that many people have heard from me. Feeding design methodologies is one of the reasons why Fedora Electronic Lab  is so attractive to many small companies.

Development behind FEL 12 focusses on adding value to the frontend design. Eclipse, being an industry standard IDE, is FEL’s main IDE for digital/embedded hardware design.

In the following blog posts, I will cover these features in depth, meanwhile you can try those plugins with yum on your Fedora 11. Only eclipse-eclox and eclipse-texlipse are not yet part of the Fedora collection. They are being reviewed #506429 and #506431 respectively.

Filed under: eclipse, eda, fedora, fpga, Free Electronic Lab, IP, perl, tcl, verilog, vhdl

Choose Tcl/Tk for EDA development

I’ve been a big Synopsys fan since I started using Design Compiler. Using DC with home-brew tcl/tk based scripts which its recent baselines have eased maintainance for EDA engineers.

That said, I would recommend Tcl/Tk for the development of opensource (digital) EDA software for the following reasons:

• new users from the digital asic designers are already familiar with Tcl – coming from proprietary software
• more chances to get contributors in, as writing plugins becomes easier (excluding all software engineerings)
• the users of opensource EDA tools are not software developers, thereby if it is a Java/Qt/GTK based application, it will be a bit hard to build a community around the EDA tool.
• (this is very important to the opensource EDA community) : more compatibilities with other Tcl/Tk based apps such as magic, irsim,netgen, xcircuit,…
• It is also help us FEL to shape an automated test framework for all these Tcl/Tk based tools.

The latter is important for the digital oriented EDA tool because we already have a handful of tcl/tk based analog tools from opencircuitdesign and Graham Petley’s standard cells, I believe Tcl/Tk is the right choice to follow as in the future, there will be more chances to have more mixed signal simulation with opensource EDA tools.

The developers of Ngspice are planning to write a Tcl/Tk based frontend for ngspice and if your software uses Tcl/Tk, we will be able to ensure several design flows with opensource EDA tools. Knowing as well the fact that Tkgate provides verilog support with a simple tcl/tk based app, it would be nice to have easy and quick scripting interface to both design and simulation with your software.

Filed under: tcl