FEL: Bug fix release of Icarus Verilog 0.9.3

The Icarus Verilog developers are pleased to announce the next stable release in the 0.9 series, version 0.9.3. Icarus Verilog is a mostly complete implementation of the hardware description language Verilog, as described in IEEE Std 1364-2005. It also includes a number of user requested extensions.
Icarus Verilog 0.9.3 improves language coverage over the previous stable release, but is primarily a bug fix release. Therefore, we recommend people using the 0.9.2 release upgrade to 0.9.3 as soon as possible. Version 0.9.3 is the recommended version for all new users.

More details, including known limitations, deviations from IEEE Std 1364-2005, can be found in the Release Notes located here.

Icarus Verilog 0.9.3 will be available soon on update-testing repositories:

# yum install iverilog --enablerepo=updates-testing

Filed under: iverilog, verilog

[FEL]: Icarus Verilog bug statistics

Cary R. published some statistics about the amount of time spent in bug fixing for the most widely used opensource verilog simulator, Icarus Verilog. I’m quoting:

Excluding the VHDL work, so far in 2009 we have had 25 invalid bug reports, 87 valid bug reports. Eight of these are still open. It took on average 12 days to fix a bug and the open bugs have been open for an average of 177 days. That attached plot shows the details much better.

Icarus Verilog development team is heading towards the release of 0.9.2, which will be realeased pretty soon. If you are encountering some other bugs on 0.9.1 (the current fedora iverilog version), please do file bug reports so that they can be fixed for the 0.9.2 release.

In the past, I’ve described how to use iverilog for post-synthesis simulation and how to access documentation quickly to ensure interoperability and other verilog variants. If you are encountering issues while dealing with FPGA and iverilog, please feel free to share it with us.

Filed under: eda, iverilog

Xilinx-icarus verilog : post synthesis simulation

Earlier, I’ve described how you could do post synthesis simulation with ghdl from a generated xilinx-based vhdl netlist. Below, you can now find how simulate with icarus verilog if that netlist was to be verilog-based:

# yum install iverilog

# -------------------------------------------------------------
postsim:
 iverilog -Wall \
   -y $(XILINXCADROOT)/verilog/src/unisims \
   -y $(XILINXCADROOR)/verilog/src/XilinxCoreLib \
   $(PROJECT)_synthesis.v $(PROJECT)_tb.v -o $(PROJECT).bin
 vvp $(PROJECT).bin
#---------------------------------------------------------------

If you like automating your verilog-based digital design flow, Fedora provides additional perl scripts for Verilog (as well for VHDL) to help you sign off different stages of your design flow. Learn more about those Perl modules by:

# yum search perl-Verilog*

# rpm -qd PACKAGE

We would like to know if you are encountering any difficulties in your custom design flow with Fedora Electronic Lab, maybe we can smooth the edges for you.

With upcoming Fedora 11, we have provided enough solutions to harden your ASIC handoff checklist.

Filed under: iverilog, xilinx