[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.

Filed under: asic, emacs, feature, fedora, Free Electronic Lab, IP, xcircuit

FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP

The picture shows the respective eclipse-plugins, which will enhance :

• frontend design
• autogeneration of documentation and maintenance of professional datasheets
• Perl/Tcl scripting (Perl modules which featured as from FEL10)
• version controlled

experience for Fedora users.

Think Methodology and not random packaging.

This is sentence that many people have heard from me. Feeding design methodologies is one of the reasons why Fedora Electronic Lab  is so attractive to many small companies.

Development behind FEL 12 focusses on adding value to the frontend design. Eclipse, being an industry standard IDE, is FEL’s main IDE for digital/embedded hardware design.

In the following blog posts, I will cover these features in depth, meanwhile you can try those plugins with yum on your Fedora 11. Only eclipse-eclox and eclipse-texlipse are not yet part of the Fedora collection. They are being reviewed #506429 and #506431 respectively.

Filed under: eclipse, eda, fedora, fpga, Free Electronic Lab, IP, perl, tcl, verilog, vhdl

Engineers should stage a patent strike

Rick Merritt shares his opinion: Engineers should stage a patent strike. He thinks it’s time for design engineers to stage an intellectual property strike.

As far as I know, some companies give bonus to Analog ASIC engineers if they initiated and maintain IP for the company. But at the same time, during this financial crisis, some companies have cancelled such bonus.

Filed under: IP