FEL: Bugfix release of Verilator 3.805

Verilator 3.805 2010/11/02

• Add warning when directory contains spaces, msg378. [Salman Sheikh]
• Fix wrong filename on include file errors, bug289. [Brad Parker]
• Fix segfault on SystemVerilog “output wire foo=0″, bug291. [Joshua Wise]
• Fix DPI export name not found, msg369. [Terry Chen]

It will soon be among your updates. Special credits go to Veripool.

Filed under: Free Electronic Lab, perl, verilator

FEL: Bugfix release of Verilog-Perl 3.304

Verilog::Language 3.304 released on 2010/10/25 fixes wrong filename on include file errors, bug289, by Brad Parker. This bug fix will soon be available among your FEL updates.

Filed under: Free Electronic Lab, perl, verilog

[FEL]: PCB Release 20100929 available

Our gEDA/gaf community is proud to release a new enhance version of the famous opensource PCB layout editor, PCB.

This release represents over 240 commits and as such this summary clearly is not complete. See the ChangeLog file for the complete list of changes.

Free Electronic Lab users can soon grab it via:

# yum install pcb --enablerepo=updates-testing

Features

• PCB can directly import (forward annotate) schematics while running.
• Many places where measurements are entered now accept units, like “5mm”, and “cm” and “in” are allowed too.
• Free Rotate Buffer added to menu
• Polygon Hole tool.
• F12 invokes the Lock tool.
• Russian translation added.
• DBUS is enabled by default when possible.
• Command-line exporters can run action scripts too.
• GTK tool tips on elements, pins, and nets.
• Command-line actions in GUIs do not require (,,) syntax.
• PCB can import footprints both in subdirectories and the named directories.
• New GCode exporter.
• Footprint files use “.fp” as the suffix; this is automatically searched for if needed.
• GTK dialogs do not show at startup unless requested.
• Stackup can be specified on the command line for command-line exporting.
• Reference card updated.
• The snap-point in pads is the center.
• The ‘s’ key toggles polygons to clear/notclear all pads and pins

Filed under: pcb

FEL: Slides from DVClub Bristol September 2010

Last week, we participated in DVClub Sept 2010: “Using Open Source Verification Tools”.

There were over 100 registrations. The feedback from the Bristol site was very good – people really enjoyed the talks and that the technology worked much better. Thank you very much to everyone who worked very hard to organize this event for European engineers, in Bristol, Cambridge and Eindhoven, with remote access too, considered  - see links below for slides.

“Verilator; fast, free, but for me?” Wilson Snyder

“Architecture For Massively Parallel HDL Simulations” Rich Porter, Art of Silicon

“Free Electronic Lab: Hardware engineering made easy” Chitlesh Goorah

“Processor verification using open source tools and the GCC regression test suite: A case study” Dr Jeremy Bennett, founder and CEO of Embecosm

Filed under: events, Free Electronic Lab, On the News

FEL at DVClub Bristol, 20 Sep 2010

We’re happy to announce Free Electronic Lab and open source EDA is the topic of the DVClub Bristol meeting, 20 September 2010, at 11:30-2PM WEST/BST. The talks will be 12-2PM (7-9AM EDT) via

• web conference
• in Bristol, England (Infineon, Great Western Court, Hunts Ground Road, Stoke Gifford, BS34 8HP)
• Cambridge, England (The ARM office in Cambridge (110 Fulbourn Road, Cambridge, CB1 9NJ)
• and Eindhoven, Netherlands.

The presentations are:

• “Verilator; fast, free, but for me?”, by Wilson Snyder, developer of Verilator.
• “Architecture For Massively Parallel HDL Simulations”, by Rich Porter from Art of Silicon.
• “Free Electronic Lab: Hardware engineering made easy”, by Chitlesh Goorah, Digital Design Engineer, ON Semiconductor and developer of Free Electronic Lab.
• “Processor verification using open source tools and the GCC regression test suite: A case study”, by Dr. Jeremy Bennett, founder and CEO of Embecosm.

We hope to see you (virtually) there. For details and to register, follow these guidelines.

This event is sponsored by ARM, Infineon, the NMI and TVS.

Filed under: DVClub, Free Electronic Lab, opencore

Floorplanning with Magic, how hard can that be ?

Alliance VLSI development cycle has stalled and there are many software compatibility issues that need to be solved before getting a proper (one that can meet the industry’s needs) digital backend flow with opensource software. Herb which was meant as a clone for Alliance VLSI will not be stable enough at the end of this year, nor I would expect some Mixed-Signal designs from it.

Since it won’t be TCL based, I doubt I would even use Herb myself. Hence, I’m investigating further on what should be done before one can design a mixed signal chip with the industry’s requirements.

Magic VLSI is fairly analog oriented, it is TCL based and it is lambda based. Since it is TCL based, it deserves credits. But being lambda based it makes it hard to go beyond 90nm process node with it since it won’t be accurate enough. Surely a timing correlation would prove this.

Magic’s 2 grid cells normally represent the length of the transistor. However, macro models of SRAM/ROM available in the LEF format include decimal points to reflect the position of different metal layers and vias. This is a major drawback with Magic VLSI.

Achieving digital implementation with Magic would certainly require new techniques about  how to use magic itself and how metrics (resistances, capacitances, switching activities,..) are extracted.

I started today with a case scenario: try to get a simple floorplan setup with some macro models. Nigel Nordsworth has kindly forwarded some Macro models. He is FEL’s test contributor for more than a year now. As mentioned above, LEF files might include X and Y positions with 3 decimal points in microns. Hence, to load the macro models, these X and Y positions should be multiplied by 1000 and thereby converting them into the nanometer scale.

Our current possible solution would be to use a Magic’s grid cell to represent 1 nm². This is not how one would normally use Magic. The complexity slope rises as all the tech files should be revisited and possibly be project dependent. Being project dependent, the solution would not be useful for the normal user. But once we can get a proper TCL package with can help us rotate the macro models and one of the 3 internal routers of magic can actually do some power routings (VDD and GND), we will present our solution for standardization.

instance_name ""
foreach instance [ cellname list instances ] {
    if { $instance == $element_name } {
         set instance_name $element_name
    }
}

select cell $instance_name
instance celldef $instance_name

regsub {\.} $xl {} xl
regsub {\.} $yl {} yl
move to $xl $yl

puts "Info: Moved the following selected Macro to ($xl,$yl)"

Using the above TCL commands just to move around the macro model I believe that a digital implementation should be feasible with Magic VLSI. But some intelligent mechanisms should be investigated about the timing and power correlations. As I wrote in the past, coupled with IRSIM we can even estimate leakage power out of the design during standby mode.

It should be exciting to design low power and low voltage designs.

Filed under: alliance, asic, magic

[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.

Filed under: asic, emacs, feature, fedora, Free Electronic Lab, IP, xcircuit

[FEL]: Recent updates are minor enhancements

The following packages have pushed (timeframe: from last week till today) to the repositories to ensure stability and extra device support.

xcircuit 3.6.164 :

• Fixed crash while creating a symbol from schematic with no component name.

ngspice rework 20 :

I’ve blogged about ngspice rework 20 fedora release 1 here. Yesterday ngspice rework 20 fedora release 3 was pushed to repositories, with improved interoperability with xcircuit. New blog post will detail that feaure. Our fedora ngspice was pulling this patch for quite some time now. Upstream (Holger Volt) improved and applied the patch to the CVS branch. While waiting for the next release perhaps ngspice rework 21, fedora users can benefit it with ngspice-20-3.

gnusim8085 1.3.5-6:

• Bug RHBZ 542945 fixed :  crash on click on the about menu

toped 0.9.51-1:

Krustev Svilen finished the workaround for the reported start-up crash with Mesa DRI on Intel(R) 945GM. The issue is described here.

Toped now have a command line option (-ogl_safe) which will force the renderer to use only basic openGL functionality. This will allow the users run the program on untested graphical platforms.

The initial diagnostic of the graphic platform is also updated to be more conservative. This will be the case until he has more clear answers from the 945GM DRI developers.

pcb 0.20091103-2

Fedora/EPEL-5′s pcb package was recompiled with dbus support enabled. Thus this allows xgsch2pcb to communicate with pcb and gschem. RFE RHBZ 541879.

vrq 1.0.67

ShakthiKannan has pushed this bug release to the repositories. Please read the ChangeLog for more details carried out by upstream.

$ rpm -qd vrq | grep ChangeLog

(new package) : emacs-irsim-mode

Arun SAG now maintains irsim-mode. It should hit mirrors in one or two days. It provides two features : indentation and syntax highlight on emacs. This will be the delight for those users who conduct event driven simulation and stuck-at fault simulation with irsim from sim netlists.

Filed under: eda, feature, fedora, Free Electronic Lab

[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

• Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
• Piecewise linear(PWL) functionality for B sources.
• Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
• New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

…

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

…

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Filed under: asic, eda, feature, fedora, Free Electronic Lab, ngspice

[FEL] Tip: Verilog lint with Emacs

Verilator has verilog lint capabilities aside its main robust functionality : Verilog code to C++/SystemC conversion.

# yum install verilator

$ verilator –lint-only mydesign.v

Coupled with verilog-mode, it can really boost productivity for the experienced designer just by adding the following to the .emacs file.

(setq verilog-linter “verilator –lint-only”)

Currently we are making a request to upstream so that vhdl-mode and verilog-mode bundled with emacs can be updated. Possibly this should be also be enabled by default.

Filed under: emacs, Free Electronic Lab, verilog