[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.

Filed under: asic, emacs, feature, fedora, Free Electronic Lab, IP, xcircuit

[FEL]: Recent updates are minor enhancements

The following packages have pushed (timeframe: from last week till today) to the repositories to ensure stability and extra device support.

xcircuit 3.6.164 :

• Fixed crash while creating a symbol from schematic with no component name.

ngspice rework 20 :

I’ve blogged about ngspice rework 20 fedora release 1 here. Yesterday ngspice rework 20 fedora release 3 was pushed to repositories, with improved interoperability with xcircuit. New blog post will detail that feaure. Our fedora ngspice was pulling this patch for quite some time now. Upstream (Holger Volt) improved and applied the patch to the CVS branch. While waiting for the next release perhaps ngspice rework 21, fedora users can benefit it with ngspice-20-3.

gnusim8085 1.3.5-6:

• Bug RHBZ 542945 fixed :  crash on click on the about menu

toped 0.9.51-1:

Krustev Svilen finished the workaround for the reported start-up crash with Mesa DRI on Intel(R) 945GM. The issue is described here.

Toped now have a command line option (-ogl_safe) which will force the renderer to use only basic openGL functionality. This will allow the users run the program on untested graphical platforms.

The initial diagnostic of the graphic platform is also updated to be more conservative. This will be the case until he has more clear answers from the 945GM DRI developers.

pcb 0.20091103-2

Fedora/EPEL-5′s pcb package was recompiled with dbus support enabled. Thus this allows xgsch2pcb to communicate with pcb and gschem. RFE RHBZ 541879.

vrq 1.0.67

ShakthiKannan has pushed this bug release to the repositories. Please read the ChangeLog for more details carried out by upstream.

$ rpm -qd vrq | grep ChangeLog

(new package) : emacs-irsim-mode

Arun SAG now maintains irsim-mode. It should hit mirrors in one or two days. It provides two features : indentation and syntax highlight on emacs. This will be the delight for those users who conduct event driven simulation and stuck-at fault simulation with irsim from sim netlists.

Filed under: eda, feature, fedora, Free Electronic Lab

[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

• Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
• Piecewise linear(PWL) functionality for B sources.
• Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
• New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

…

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

…

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Filed under: asic, eda, feature, fedora, Free Electronic Lab, ngspice

[draft]: Fedora Electronic Lab 12′s Flyer

During Fedora 12 ‘Constantine’ development cycle, we have improved the existing FEL platform with multiple updates and new features (just to name a few):

• Logic optimization with espresso.
• tclspice support for ngspice.
• 8051 and 8085 simulators.
• Collaborative development and code review methodologies.
• Stability on 64-bit architectures during long runtime (big digital projects).
• ……..

A Fedora Electronic Lab 12 flyer has been drafted to encourage users to test the upcoming test releases before the general public release.

In the upcoming days, I’ll post the Release Notes document of FEL-12. It already has 26 pages

Filed under: eda, feature, fedora, Free Electronic Lab

FEL: Icarus Verilog: more than simulator

This blog post highlights the VPI bug fix and some hidden features of iverilog which most verilog users are not aware. Fedora proposes Icarus Verilog for verilog simulation. The related documentation of iverilog and examples can be found via

• man vvp
• man iverilog
• man iverilog-vpi
• and rpm -qld iverilog

To install Icarus Verilog on Fedora:

# yum install iverilog

Icarus Verilog is available on the Fedora Electronic Lab livedvd.

Keys features of Icarus Verilog

All the mentioned documentation below can be found via

$ rpm -qld iverilog | grep DOC

Use any text editor of your choice to open them.

• Supports attributes to control synthesis

More details : attributes.txt

• Supports some extensions of verilog variant: SystemVerilog

More details : extensions.txt

• FPGA code generator

More details : fpga.txt

• Compatibility with the Cadence PLI module

More details : cadpli.txt

• Accessible Standard Verilog-A Mathematical Constants.

More details : va_math.txt

• VPI interface supporting trace

Environment variable : VPI_TRAC

More details : vpi.txt

# yum install iverilog-devel

Filed under: feature, fedora, Free Electronic Lab, verilog

FEL Spin: Switching to Gnome (desktop ks)

During the Spin session at FUDCon Berlin, I expressed my intention to  switch FEL spin from kde-based to gnome-based. I have already made the  necessary changes to FEL’s kickstart file.

My tests were successful and I am pleased with it.

Reason for the switch
Simple, my laptop (only machine I have) struggles a lot with KDE4. I am a KDE user and even a KDE booth staff for CEBIT 2007 in Germany. If I personally cannot test and qualify the spin before the release, we can’t ship it.

What does it mean for the Spin SIG ?
Nothing particularly as the dependency of the FEL spin is switched to  the default Fedora Desktop kickstart.

What does it mean for the User ?
The users are the only one which will see the difference. But since Fedora Developers spent a lot of resources on the desktop livecd (+ the fedora features) compared to the KDE upstream project, FEL users will benefit with better power management, better boot time, better distribution integration and any items from the fedora feature list.

What does it mean for the spin maintainer ?
Nothing particularly. It is just a one-line change in FEL’s ks. Since the dependency is heavily tested by the Fedora QA team, I can focus only on the goals/objectives of FEL. Since, FEL apps are added to comps, it is even easier for me to maintain the spin.

I am personnally affected by this switch, since I have never used Gnome before. However the objective is not about whether gnome or kde is good, how to focus on the electronic ASIC design methodologies which opensource software can provide. That said, desktop environments such as LXDE and XFCE are automatically discarded for FEL (at least
for the next 2/3 fedora releases) since

• Fedora XFCE spin’s history shows it was either not ready for the official fedora release or not released.
• Fedora LXDE spin is new and the first official fedora board approved spin will most probably be for F-12.

As a spin maintainer, I care a lot about the spin’s dependencies. If the dependencies failed, FEL will not be released.

I am sorry for any inconvenience that may cause you however if you want to help us, please have a look at this dynamic todo list.

I want to thank RexDieter and KevinKofler for their tremendous help since the beginning. Rex worked hard on optimizing KDE before F-11 release, at that time I was already seriously considering the switch. Rex’s optimization worked for me and thereby FEL 11 was KDE based.

Filed under: feature, fedora, Free Electronic Lab, gnome, kde

FEL is too complex for my head

Since FEL8′s release, I keep a notebook to write anything related to FEL before I forget it. This entails my list of FEL todos, new EDA solutions, items I should work on, people whom I should contact for guidance, …



Today this notebook has 47 pages written by me and need my attention. After any FEL official release, I go back again filtering my notebook for items to work on. Since our release cycle is only 6 months, we had to stick on a fair number of items to work on. These items on jotted down into this gantt diagram. I would appreciate if you could have sometime to go through it and help us out if you can.

I also have my measurements on that notebook. I have started writing a tech report on some testing I’m carrying out with respect to FEL’s chip testing solutions. I should find some time to complete that tech report. However FEL is becoming too complex to maintain both software and the overall EDA solutions. Looking back to my notebook again, the number of block diagrams I have drawn in order to explain others what we actually do. One block diagram seems to be self-explanatory on the massive work done behind FEL. I guess I have to draw it on dia and publish it.

Filed under: feature, Free Electronic Lab

Fast User Switching since F7

Whether you are a fedora user or not, “Fast User Switching” was a feature during F7′s (moonshine) release.

If you are writing an article (whether on your blog or somewhere else) about any “new features” in the open source community, please don’t say that fedora’s is missing it without enough proof otherwise!

I never thought that lack of software updates might severely affects end users’ mind.

Filed under: feature, fedora