Xilinx-icarus verilog : post synthesis simulation

Earlier, I’ve described how you could do post synthesis simulation with ghdl from a generated xilinx-based vhdl netlist. Below, you can now find how simulate with icarus verilog if that netlist was to be verilog-based:

# yum install iverilog

# -------------------------------------------------------------
postsim:
 iverilog -Wall \
   -y $(XILINXCADROOT)/verilog/src/unisims \
   -y $(XILINXCADROOR)/verilog/src/XilinxCoreLib \
   $(PROJECT)_synthesis.v $(PROJECT)_tb.v -o $(PROJECT).bin
 vvp $(PROJECT).bin
#---------------------------------------------------------------

If you like automating your verilog-based digital design flow, Fedora provides additional perl scripts for Verilog (as well for VHDL) to help you sign off different stages of your design flow. Learn more about those Perl modules by:

# yum search perl-Verilog*

# rpm -qd PACKAGE

We would like to know if you are encountering any difficulties in your custom design flow with Fedora Electronic Lab, maybe we can smooth the edges for you.

With upcoming Fedora 11, we have provided enough solutions to harden your ASIC handoff checklist.

Filed under: iverilog, xilinx

Xilinx-GHDL : post synthesis simulation

Those who like ghdl and gtkwave frequently ask the same question while working with Xilinx FPGAs. “How can one do post synthesis with unisim libraries ?”

Below you will find part of a makefile which automates this post synthesis simulation with ghdl and gtkwave. I assume that you have already installed the xilinx webpack by yourself. Fedora 10 has the latest gtkwave version with tcl and tab support to improve your verification methodologies. Happy design on your Fedora.

  
# ----------------------------------------------------
PROJECT       = cst299
XILINXCADROOT = /opt/xilinx/ISE/10.1.03_K.39/ISE

UNISIMS       = $(XILINXCADROOT)/vhdl/src/unisims

postsyn: libunisim postsyn_sub compileTb runTb

libunisim:
 rm -rf unisim && mkdir -p unisim
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  $(UNISIMS)/unisim_VCOMP.vhd    \
  $(UNISIMS)/unisim_VPKG.vhd     \
  $(UNISIMS)/unisim_SMODEL.vhd   \
  $(UNISIMS)/unisim_virtex5_SMODEL.vhd
 # http://ghdl.free.fr/ghdl/Using-vendor-libraries.html
 cp -p $(UNISIMS)/unisim_VITAL.vhd unisim_VITAL.vhd
 sed -i  -e "s|variable Write_A_Write_B|--variable Write_A_Write_B|" \
  -e "s|variable Read_A_Write_B|--variable Read_A_Write_B|"   \
  -e "s|variable Write_A_Read_B|--variable Write_A_Read_B|"   \
  -e "s|variable Write_B_Write_A|--variable Write_B_Write_A|" \
  -e "s|variable Read_B_Write_A|--variable Read_B_Write_A|"   \
  -e "s|variable Write_B_Read_A|--variable Write_B_Read_A|"   \
  unisim_VITAL.vhd
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  --warn-no-vital-generic unisim_VITAL.vhd

postsyn_sub:
 rm -rf work && mkdir -p work
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  $(PROJECT)\_synthesis.vhd

compileTb:
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb.vhd
 # Compile Testbench
 ghdl -m --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb

runTb:
 # Run Testbench
 ghdl -r --workdir=work \
  $(PROJECT)\_tb --vcd=$(PROJECT)_postsyn.vcd \
  --stop-time=200ns
#---------------------------------------------------------------
Then use gtkwave to view the waveform.

Filed under: fpga, ghdl, gtkwave, unisim, xilinx