F-14 – libsys_cpt.so error with Quartus 11.0

While installing Quartus 11 on Fedora 14, I hit this small issue:

quartus: error while loading shared libraries: libsys_cpt.so: cannot enable executable stack as shared object requires: Permission denied

Solution (as root):

$ cd /opt/altera/11.0/quartus/linux
$ execstack -c libstdc++-libc6.2-2.so.3 libicudata.so.34 libsys_cpt.so

Filed under: altera, fpga, quartus

FEL12: Eclipse for reusable Embedded/VHDL/Verilog IP

The picture shows the respective eclipse-plugins, which will enhance :

• frontend design
• autogeneration of documentation and maintenance of professional datasheets
• Perl/Tcl scripting (Perl modules which featured as from FEL10)
• version controlled

experience for Fedora users.

Think Methodology and not random packaging.

This is sentence that many people have heard from me. Feeding design methodologies is one of the reasons why Fedora Electronic Lab  is so attractive to many small companies.

Development behind FEL 12 focusses on adding value to the frontend design. Eclipse, being an industry standard IDE, is FEL’s main IDE for digital/embedded hardware design.

In the following blog posts, I will cover these features in depth, meanwhile you can try those plugins with yum on your Fedora 11. Only eclipse-eclox and eclipse-texlipse are not yet part of the Fedora collection. They are being reviewed #506429 and #506431 respectively.

Filed under: eclipse, eda, fedora, fpga, Free Electronic Lab, IP, perl, tcl, verilog, vhdl

Mentor’s webinar about FPGA Synthesis techniques

This morning I attended Mentor Graphics’s webinar about FPGA Synthesis, by Roger Do and Robert Jeffery.

Synthesis is a stage in the design flow that I personally give a lot of attention to the reports and the constraints. I am always excited about Synthesis. It is a moment that the designer and the synthesis tool share a bond. The webinar was fine and the key items covered were

• Register retiming
• Resource sharing
• Physical-aware synthesis
• Incremental synthesis
• Interconnect delays

From my perspective, the webinar was not too FPGA oriented as the webinar’s title suggested but covered common elements that one will also encounter in ASIC design. I was hoping to learn more about extra features that a third-party EDA vendor might provide that the FPGA providers don’t.

At the end, I asked a question about how the TCL scripting commands/arguments. From my point of view, the more there are tools from different vendors in a design flow the more complex is to automate the flow by scripting. Hence I wanted to know more about how the learning curve is when scripting with a third-party synthesis tool for FPGA design. My question was taken as what are the benefits of scripting, but not how difficult would it be for learning different commands/arguments from different vendors which do more or less the same task.

However, I really enjoy the webinar and thank MentorGraphics for their bi-weekly webinars. I am looking forward for the next webinar about CDC (Clock Domain Crossing).

I also participated in their poll. One of the questions on the poll was about which vendor’s FPGA I am using. I am always impressed to see in such poll that 2/3 of the participants choose Xilinx’s FPGA over Altera’s FPGA. I have not yet understood the reason behind it. One of the reasons I would choose Altera’s FPGA is because their constraints are in the SDC format, whereas Xilinx uses its own. It reassures me about the certainty of the constraints I want to apply. Hence,this ensures a quicker prototyping for a junior ASIC guy like me who visits the FPGA world.

CDC (Clock Domain Crossing)

Filed under: fpga, mentor graphics

A junior ASIC Guy Visits An FPGA World

The title of this blog post was copied from Harry Gries’s blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior.

Harry’s observations are oriented towards the “raw” design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and work hard to satisfy design tools. But in the FPGA environment, the design tools provide an even more automated work flow from frontend to backend. Physical design sometimes (depending on the size of the design) seems to take a few minutes. I have seen people even skip the entire the physical design, unless there is a violation somewhere.

I had a few FPGA projects to handoff and though they were for some different medium-sized companies, sometimes I felt that project managers and reviewers were not serious enough like in ASIC environment. I got a few remarks for my VHDL designs which sometimes coming from a senior FPGA designer shocked me. It is true as well that FPGA design was not their prime development base.

One of those remarks which till now I have not really understood the reason between it and why my reasoning was not valid. It concerned my FSMs. They had “next-state” decoding and “output” decoding into two separate VHDL processes. My reasoning which Altera’s appplication notes implies will restrict the synthesis tool from sharing resources with other blocks. The remark I got, during a code review, was “I never seen that in my 12 years career, clean this”. I am still eager to know what advantage will my design have while combining these two processes.

I also got the most chaotic code review experience with other FPGA designers. VHDL code review was left incomplete from my point of view and discarded parts of code review with respect to switching rates, power, … due to lack of time. I was expecting a thorough code review for an optimal the sign-off and hand-off like I used to see with ASIC design teams.

I’m sure this is not true in every FPGA design team. What I was to say here is that during the excursion to the FPGA world, the strict discipline routine one has in ASIC environment just fades away. How quickly? I think it depends on the FPGA design team. I could even feel how disconnected the small companies are from the EDA vendors. However, I wish to get myself involved with a “real” high-performance FPGA based design team to see how discipline they are

While these are issues I personally encountered, I am trying to get Fedora Electronic Lab enough collaborative solutions so that small companies can at least have a decent code review, project hand-off and make FPGA designers happy.

Filed under: asic, fpga

Xilinx-icarus verilog : post synthesis simulation

Earlier, I’ve described how you could do post synthesis simulation with ghdl from a generated xilinx-based vhdl netlist. Below, you can now find how simulate with icarus verilog if that netlist was to be verilog-based:

# yum install iverilog

# -------------------------------------------------------------
postsim:
 iverilog -Wall \
   -y $(XILINXCADROOT)/verilog/src/unisims \
   -y $(XILINXCADROOR)/verilog/src/XilinxCoreLib \
   $(PROJECT)_synthesis.v $(PROJECT)_tb.v -o $(PROJECT).bin
 vvp $(PROJECT).bin
#---------------------------------------------------------------

If you like automating your verilog-based digital design flow, Fedora provides additional perl scripts for Verilog (as well for VHDL) to help you sign off different stages of your design flow. Learn more about those Perl modules by:

# yum search perl-Verilog*

# rpm -qd PACKAGE

We would like to know if you are encountering any difficulties in your custom design flow with Fedora Electronic Lab, maybe we can smooth the edges for you.

With upcoming Fedora 11, we have provided enough solutions to harden your ASIC handoff checklist.

Filed under: iverilog, xilinx

Xilinx-GHDL : post synthesis simulation

Those who like ghdl and gtkwave frequently ask the same question while working with Xilinx FPGAs. “How can one do post synthesis with unisim libraries ?”

Below you will find part of a makefile which automates this post synthesis simulation with ghdl and gtkwave. I assume that you have already installed the xilinx webpack by yourself. Fedora 10 has the latest gtkwave version with tcl and tab support to improve your verification methodologies. Happy design on your Fedora.

  
# ----------------------------------------------------
PROJECT       = cst299
XILINXCADROOT = /opt/xilinx/ISE/10.1.03_K.39/ISE

UNISIMS       = $(XILINXCADROOT)/vhdl/src/unisims

postsyn: libunisim postsyn_sub compileTb runTb

libunisim:
 rm -rf unisim && mkdir -p unisim
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  $(UNISIMS)/unisim_VCOMP.vhd    \
  $(UNISIMS)/unisim_VPKG.vhd     \
  $(UNISIMS)/unisim_SMODEL.vhd   \
  $(UNISIMS)/unisim_virtex5_SMODEL.vhd
 # http://ghdl.free.fr/ghdl/Using-vendor-libraries.html
 cp -p $(UNISIMS)/unisim_VITAL.vhd unisim_VITAL.vhd
 sed -i  -e "s|variable Write_A_Write_B|--variable Write_A_Write_B|" \
  -e "s|variable Read_A_Write_B|--variable Read_A_Write_B|"   \
  -e "s|variable Write_A_Read_B|--variable Write_A_Read_B|"   \
  -e "s|variable Write_B_Write_A|--variable Write_B_Write_A|" \
  -e "s|variable Read_B_Write_A|--variable Read_B_Write_A|"   \
  -e "s|variable Write_B_Read_A|--variable Write_B_Read_A|"   \
  unisim_VITAL.vhd
 ghdl -a --work=unisim --workdir=unisim \
  --ieee=synopsys -fexplicit     \
  --warn-no-vital-generic unisim_VITAL.vhd

postsyn_sub:
 rm -rf work && mkdir -p work
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  $(PROJECT)\_synthesis.vhd

compileTb:
 ghdl -a --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb.vhd
 # Compile Testbench
 ghdl -m --work=work -Punisim --workdir=work \
  --ieee=synopsys -fexplicit \
  --warn-no-vital-generic $(PROJECT)\_tb

runTb:
 # Run Testbench
 ghdl -r --workdir=work \
  $(PROJECT)\_tb --vcd=$(PROJECT)_postsyn.vcd \
  --stop-time=200ns
#---------------------------------------------------------------
Then use gtkwave to view the waveform.

Filed under: fpga, ghdl, gtkwave, unisim, xilinx

Windows free and Linux you need a Paid subscription

If you buy a FPGA development kit from any Vendor of your choice, you will need to program your VHDL/Verilog code into the FPGA.

The EDA software to program the FPGA is vendor specific as each FPGA has its own characteristics(number of pins,capacitance values, voltage per bank, number of Logic Elements…).

However, these FPGA vendors give away their EDA tool for free as Web Edition for:

• windows together with the tcl-based Modelsim
• linux : the web edition can be downloaded for free and used for a 30 days evaluation only.

This is weird for the linux community because the mindset is the other way round. This explains also that software is ridiculous for hardware vendors, but still they can only attract customers via the features of their EDA tools. These features include :

• technology of the FPGA device
• improvement in their synthesis algorithms
• report generation of the compilation and place and route/fitting.
• Power,area,retiming, inferred logic
• IP core support
• FPGA device migration of different families
• … the list goes on

This is among the reasons why opensource EDA tools for FPGA only existed for ONE month. It is currently fairly impossible with opensource EDA tools to achieve both frontend and backend design for FPGA in a single day. It is impossible for opensource EDA contributors like me to answer these demands.

While the current semiconductor industry trend is migrating from ASIC design to FPGA based design, the frontend designers should now re-adapt their VHDL code. This change does not only imply changing EDA tools, but also change VHDL coding mindset. This is a hard thing to do, believe me. You will only see those issues when the compilation ending with more than 15000 warnings and numerous vendor specific rules have not been obeyed.

I came up with a theory the other day. Such migration will certainly results in internal crisis between LIB&IP department and frontend digital designers. If you are one of those, buy yourself a “How not to stress” book.

Filed under: fpga

Attention to the detail

Simon Bloch of Mentor Graphics said he was misunderstood and that the title of the article EDA tools for FPGAs running out of gas by Mark LaPedus should rather be : EDA tools are giving gas to FPGAs.

Isn’t it useless from a senior ? EDA tools are meant to give gas to any electronic design (whether FPGA or ASIC). This is the main purpose of EDA tools : aid and improve. Thereby it doesn’t restrict to FPGA only.

However adding “new versions of” to “EDA tools are giving gas to FPGAs” such as “new versions of EDA tools are giving gas to FPGAs” sounds to be more appropriate. Thereby, reminding people to update their tools or buy new EDA software licenses for FPGA design.

Filed under: fpga