[FEL]: gplcver crash fix and openocd update

Shakthi updated gplcver to fix a crash upon launch.

Dean Glazeski updated openocd to 0.5.0.

 

Filed under: fedora, Free Electronic Lab

the missing -ldl

export CFLAGS="%{optflags} -ldl -lpthread"

to fix

/usr/bin/ld: dynload.o: undefined reference to symbol  'dlsym@@GLIBC_2.2.5'
/usr/bin/ld: note: 'dlsym@@GLIBC_2.2.5' is defined in DSO
/lib64/libdl.so.2 so try adding it to the linker command line
/lib64/libdl.so.2: could not read symbols: Invalid operation
collect2: ld returned 1 exit status

Filed under: fedora, gerbv

Restoring Electronics-menu in Gnome3

With Gnome 3 shipped with Fedora 15, the menu “electronics” is no longer available on Fedora 15′s gnome-menu.

It was rather annoying for me, as this custom “Electronics” menu remained the first thing that non-linux users would look at if they want to embrace Free(Fedora) Electronic Lab.

Finally, I found how to fix it. It seems that the directory /etc/xdg/menus/application-merged became /etc/xdg/menus/application-gnome-merged.

$ mkdir  /etc/xdg/menus/applications-gnome-merged
$ ln -s /etc/xdg/menus/applications-merged/electronics.menu /etc/xdg/menus/applications-gnome-merged/electronics.menu

The “electronics-menu” package will soon be updated to reflect this fix on Fedora 15.

Filed under: fedora, Free Electronic Lab, gnome

[FEL]: Standard Cell characterisation – part two

Xcircuit 3.6 series brings on technology library support, which enables anyone to maintain customed analog or digital IPs, independent of the schematic design. This powerful feature, coupled with ngspice, helps the designer to maintain their spice commands within the testbench schematic. It will automatically extracts the spice netlists with the subcircuits included, then from the tcl console simulate the design.

However this was not working out of the box and the user needed to patch ngspice. Since ngspice rework 17, Fedora’s ngspice was patched accordingly. But with ngspice rework 19, it broke. This week Holger Volgt improved the patch and merge it to ngspice cvs branch.

This blog post will briefly show a testcase about how to invoke ngspice within Xcircuit directly.

Launch Xcircuit and load your design. Here, I’ll take a simple invertor as example. Then launch the Tcl console from the file menu and type

::xcircuit::spice start

If you encounter this error, you are certainly using an older version of ngspice.

There is already an update in the fedora repositories which fixes this issue.

On the screenshot below, you can see the invertor in a test situation alongside spice commands for the simulation. Hence there is no need to maintain extra file or makefile to launch SPICE simulation. Everything is launched and saved by Xcircuit in a postscript format.

::xcircuit::spice start

(extracts the spice netlist and sets the initial condiction.)

::xcircuit::spice run

(executes the simulation)

::xcircuit::spice send “plot v(Vin) v(Vout)”

(sends the plot command to ngspice and displays the plot)

Arun SAG has recently filed a package review request for emacs-spice-mode. Once approved and pushed to Fedora repositories, you can execute spice simulations within emacs as well.

Filed under: asic, emacs, feature, fedora, Free Electronic Lab, IP, xcircuit

[FEL]: Recent updates are minor enhancements

The following packages have pushed (timeframe: from last week till today) to the repositories to ensure stability and extra device support.

xcircuit 3.6.164 :

• Fixed crash while creating a symbol from schematic with no component name.

ngspice rework 20 :

I’ve blogged about ngspice rework 20 fedora release 1 here. Yesterday ngspice rework 20 fedora release 3 was pushed to repositories, with improved interoperability with xcircuit. New blog post will detail that feaure. Our fedora ngspice was pulling this patch for quite some time now. Upstream (Holger Volt) improved and applied the patch to the CVS branch. While waiting for the next release perhaps ngspice rework 21, fedora users can benefit it with ngspice-20-3.

gnusim8085 1.3.5-6:

• Bug RHBZ 542945 fixed :  crash on click on the about menu

toped 0.9.51-1:

Krustev Svilen finished the workaround for the reported start-up crash with Mesa DRI on Intel(R) 945GM. The issue is described here.

Toped now have a command line option (-ogl_safe) which will force the renderer to use only basic openGL functionality. This will allow the users run the program on untested graphical platforms.

The initial diagnostic of the graphic platform is also updated to be more conservative. This will be the case until he has more clear answers from the 945GM DRI developers.

pcb 0.20091103-2

Fedora/EPEL-5′s pcb package was recompiled with dbus support enabled. Thus this allows xgsch2pcb to communicate with pcb and gschem. RFE RHBZ 541879.

vrq 1.0.67

ShakthiKannan has pushed this bug release to the repositories. Please read the ChangeLog for more details carried out by upstream.

$ rpm -qd vrq | grep ChangeLog

(new package) : emacs-irsim-mode

Arun SAG now maintains irsim-mode. It should hit mirrors in one or two days. It provides two features : indentation and syntax highlight on emacs. This will be the delight for those users who conduct event driven simulation and stuck-at fault simulation with irsim from sim netlists.

Filed under: eda, feature, fedora, Free Electronic Lab

[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

• Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
• Piecewise linear(PWL) functionality for B sources.
• Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
• New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

…

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

…

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Filed under: asic, eda, feature, fedora, Free Electronic Lab, ngspice

[FEL]: Circuit simulation improved

Paolo Nenzi, Dietmar, Holger Vogt and Robert Larice have contributed to the enhanced stability with the new ngspice rework 20 release. ngspice rework 20 has already been pushed to fedora stable repositories with the following enhancements:

• Model names can start with a number like 1N4001
• .global command reinstated (was disabled)
• Error messages now display line number of input deck
• [feature]: .measure with tran, ac and dc (not yet complete, e.g DERIV is missing)
• [feature]: sysinfo command added
• [device]: Updated bsim4 model to BSIM 4.6.5
• [device]: Added PWL functionality for B sources

Currently Holger Vogt is kindly looking after my variable instantiation feature request for the .measure command. Hopefully after some testing, we can push another release to the stable repositories so that fedora users can largely benefit from it as soon as possible. I will write another blog post to demonstrate how to use this small but valuable feature.

Al Davis, who is working behind gnucap, is considering system-c plugins for gnucap, probably without their run-time package. Gnucap provides a lot of the needed run time support already. It might be all that is needed is to map the interface. That said, we will have to update fedora gnucap package to the latest development snapshots with the help of Rakesh Pandit (current fedora gnucap maintainer). This will give fedora users the chance to use gnucap plugins and latest enhancements over the current 0.35 stable repositories. This deserves another blog post .

Arun Sag is working on pushing some emacs mode to the fedora repositories. Among these emacs modes, there are irsim-mode and and spice-mode (see the above screenshot). Many users will enjoy the look-and-feel on their fedora emacs. I’m taking the opportunity to remind Fedora users that irsim has stuck-at fault simulation and power estimation capabilities.

Filed under: eda, emacs, fedora, Free Electronic Lab, gnucap, ngspice

[FEL]: Verilog::Language update to 3.222 on Fedora

The perl-Verilog-Perl will now obsolete perl-Verilog as a result of a Fedora packaging naming convention.

Thanks to Wilson Snyder, the version 3.222 was just pushed to Fedora Testing repositories with the following bug fixes.

• Fix missing ; in ContAssign::verilog_text, bug177. [Nicolas Wilhelm]
• Fix multi-dimensional arrayed typedefs, bug183. [Vesselin Kavalov]
• Fix “assert () else” action_blocks. [Vesselin Kavalov]
• Fix typedef scoping under anonymous begin blocks.
• Fix `define argument mis-replacing system task of same name, bug191.
• Fix SystemPerl hitting “undefined find_interface…” in 3.220.
• Fix erroring on strings with backslashed newlines, bug168. [Pete Nixon]
• Fix compile error on RHEL3 with gettext, bug169. [Marek Rouchal]
• Fix line number miscounting with `pragma.
• Add parsing of “assign”, including SigParser::contassign callback, Netlist::ContAssign object, and related accessors.
• Several code speedups to vhier, Verilog::Netlist, and the parsers.
• Add Preproc::getall to fetch all text instead of line-by-line.
• Add Parser::new(use_cb_{name}=>0) option to speed parsing.
• Add SigParser/Netlist::new(use_vars=>0) option to speed parsing.
• Fix deep defines causing flex scanner overflows. [Brad Dobbie]
• Fix preprocessing commas in deep parameterized macros. [Brad Dobbie]
• Fix Preproc::defSubstitute not being called on parameterized macros.
• Fix Perl 5.8.8 compile error, bug115. [Marek Rouchal]

Filed under: fedora, perl

Some Licenses kill opensource mechanical design flows

Electronic design is about design flows, rather than point software. Multiple software are needed for achievement multiple design flows.

However when one software breaks, the whole design flow becomes pointless. This is why we pay great attention to the design flows under the FEL collection.

For the real life, one might also need software for the mechanical body design. The current and widely used opensource mechanical design tool, OpenCascade suffer from licensing issues with its redistribution. The OpenMoko design team uses Heekscad. The latter requires a dependency on OpenCascade. Without OpenCascade in Fedora repositories, Heekscad will not pass Fedora package review.

This is a major blocker for anyone who wants to create a Fedora Spin for mechanical design. This licensing issue limits Fedora from shipping them.

Filed under: fedora

[FEL]: DIA for System Design and documentation

Dia is known to seduce some system level designers and is used to describe different block levels for embedded design.

Fedora has just received some additional shapes for digital blocks which will improve user documentation experience, through neat functional diagram drawn by dia. They should reach fedora repositories in a day or two.

Installation:

# yum install dia-Digital dia-CMOS dia-electronic dia-electric2

Filed under: artwork, fedora, Free Electronic Lab