Mentor’s webinar about FPGA Synthesis techniques

This morning I attended Mentor Graphics’s webinar about FPGA Synthesis, by Roger Do and Robert Jeffery.

Synthesis is a stage in the design flow that I personally give a lot of attention to the reports and the constraints. I am always excited about Synthesis. It is a moment that the designer and the synthesis tool share a bond. The webinar was fine and the key items covered were

• Register retiming
• Resource sharing
• Physical-aware synthesis
• Incremental synthesis
• Interconnect delays

From my perspective, the webinar was not too FPGA oriented as the webinar’s title suggested but covered common elements that one will also encounter in ASIC design. I was hoping to learn more about extra features that a third-party EDA vendor might provide that the FPGA providers don’t.

At the end, I asked a question about how the TCL scripting commands/arguments. From my point of view, the more there are tools from different vendors in a design flow the more complex is to automate the flow by scripting. Hence I wanted to know more about how the learning curve is when scripting with a third-party synthesis tool for FPGA design. My question was taken as what are the benefits of scripting, but not how difficult would it be for learning different commands/arguments from different vendors which do more or less the same task.

However, I really enjoy the webinar and thank MentorGraphics for their bi-weekly webinars. I am looking forward for the next webinar about CDC (Clock Domain Crossing).

I also participated in their poll. One of the questions on the poll was about which vendor’s FPGA I am using. I am always impressed to see in such poll that 2/3 of the participants choose Xilinx’s FPGA over Altera’s FPGA. I have not yet understood the reason behind it. One of the reasons I would choose Altera’s FPGA is because their constraints are in the SDC format, whereas Xilinx uses its own. It reassures me about the certainty of the constraints I want to apply. Hence,this ensures a quicker prototyping for a junior ASIC guy like me who visits the FPGA world.

CDC (Clock Domain Crossing)

Filed under: fpga, mentor graphics

Thank you, Cadence and Mentor Graphics

Cadence and Mentor Graphics have both announced on the same day (4/12/2008) [1] [2]that Open Verification Methodology is available under the Apache 2 license.

While thousands of verification engineers are already using it, now if OVM gets into Fedora repositories, we will be providing industry-class verification tools for our FEL users. OVM is maintained by Cadence and Mentor Graphics.

Believe me or not, this is one step forward for the Fedora Electronic Users to meet interoperability. However, till now I haven’t seen an opensource systemverilog tool that supports it.

I have just submitted OVM for package review, while hoping to get OVM into Fedora repositories in the upcoming days.

Filed under: cadence, Free Electronic Lab, mentor graphics, systemverilog