Free Electronic Lab

Opensource EDA software development, some thoughts about the EDA/Semiconductor industry and Mixed-signal integrated circuit design

Nedit’s Ctrl-y for emacs

Nedit has a very cool feature and I’ve even seen people using gvim have something similar. However emacs for some reason doesn’t. Is it because they don’t have users of their same field of application? Well who knows.

The feature in question that with Ctrl-y on Nedit one can open a file whose filename and path are listed in a text file just by placing the cursor on that
filename. e.g

#----------------------
#!/usr/bin/tclsh
source $(SCRIPTS_HOME)/definitions.tcl
....
#----------------------

After several nights roaming online for a possible solution with emacs, I ended thinking that there is no generic for this. Hence I ended up writing the following lisp code myself with my 4-hours experience with lisp.

The objective is there is an environmental variable for each projects’ path and that each has specific technology files (LEF,Liberty(ccs,ecsm,…) for pads, sram, rom, analog modules, …… One should be able to open the $(SCRIPTS_HOME)/definitions.tcl (with a shortcut i.e Ctrl-Y) within emacs itself , instead of ctrl-x-f ?

;;
;; Nedit file open with control-y
;;
(defun cgo-open-this-file (arg)
  "Copy lines (as many as prefix argument) in the kill ring"
  (interactive "p")

  ;; select whole word
  (let (b1 b2)
    (skip-chars-backward "^<>“[\"‘")
    (setq b1 (point))
    (skip-chars-forward "^<>”]\"’")
    (setq b2 (point))
    (set-mark b1))

  ;; grab selected word and start processing it
  (setq filename
        (if (and transient-mark-mode mark-active)
            (buffer-substring-no-properties (region-beginning) (region-end))
          (thing-at-point 'symbol)))

  ;; identify a environmentalvariable
  (setq envvar (replace-regexp-in-string ".*$(" "" filename))
  (setq envvar (replace-regexp-in-string ").*" "" envvar))
  (setq envvar (getenv envvar))
  (message "envvar %s" envvar)

  ;; replacing the environmental variable
  (setq envvar_replacement (replace-regexp-in-string "\$(.*)" envvar filename))
  (message "file %s" envvar_replacement)
  (find-file envvar_replacement)
)

;; optional key binding
(global-set-key "\C-y" 'cgo-open-this-file)

This code can be improved to support multiple env variables or any thing you would like, However it works and suits my application. Feel free to post a better solution :)

Filed under: eda, emacs

[FEL]: Recent updates are minor enhancements

The following packages have pushed (timeframe: from last week till today) to the repositories to ensure stability and extra device support.

xcircuit 3.6.164 :

  • Fixed crash while creating a symbol from schematic with no component name.

ngspice rework 20 :

I’ve blogged about ngspice rework 20 fedora release 1 here. Yesterday ngspice rework 20 fedora release 3 was pushed to repositories, with improved interoperability with xcircuit. New blog post will detail that feaure. Our fedora ngspice was pulling this patch for quite some time now. Upstream (Holger Volt) improved and applied the patch to the CVS branch. While waiting for the next release perhaps ngspice rework 21, fedora users can benefit it with ngspice-20-3.

gnusim8085 1.3.5-6:

  • Bug RHBZ 542945 fixed :  crash on click on the about menu

toped 0.9.51-1:

Krustev Svilen finished the workaround for the reported start-up crash with Mesa DRI on Intel(R) 945GM. The issue is described here.

Toped now have a command line option (-ogl_safe) which will force the renderer to use only basic openGL functionality. This will allow the users run the program on untested graphical platforms.

The initial diagnostic of the graphic platform is also updated to be more conservative. This will be the case until he has more clear answers from the 945GM DRI developers.

pcb 0.20091103-2

Fedora/EPEL-5′s pcb package was recompiled with dbus support enabled. Thus this allows xgsch2pcb to communicate with pcb and gschem. RFE RHBZ 541879.

vrq 1.0.67

ShakthiKannan has pushed this bug release to the repositories. Please read the ChangeLog for more details carried out by upstream.

$ rpm -qd vrq | grep ChangeLog

(new package) : emacs-irsim-mode

Arun SAG now maintains irsim-mode. It should hit mirrors in one or two days. It provides two features : indentation and syntax highlight on emacs. This will be the delight for those users who conduct event driven simulation and stuck-at fault simulation with irsim from sim netlists.

Filed under: eda, feature, fedora, Free Electronic Lab

[FEL]: Standard Cell characterisation – part one

Both xcircuit and ngspice has been updated for Fedora/EPEL-5 last week with some key features to boost productivity for standard cell characterisation. I’ll explain briefly in two blog posts, thus this one is the first post.

Last week, Fedora users have updated their ngspice rework 19 to rework 20 (20-1.fc12), with the following key highlights :

  • Updated BSIM4 code to BSIM 4.6.5 in accordance to this document.
  • Piecewise linear(PWL) functionality for B sources.
  • Support of 5-terminal bjt’s in subckt’s by prepending subckt name (similar things should be made for 5-7 terminal mos transistors, like soi models).
  • New measurement code, which is the most awaited feature for standard cell characterisation.

Currently the measurement code is still undocumented, so I hope this blog post will help ngspice users understand with their baby steps with ngspice’s .meas command. Though it follows the same syntax as HSpice, it still not yet complete. Hopefully the next ngspice releases will smooth the edges.

.meas command

Anyone who is characterising standard cells can now use .meas command and it surely helps to maintain an automatic flow.

For the sake of simplicity, I’ll cover a transient simulation as example, however one can also use it for voltage transfer characteristic of the cell.

.tran 0.1 18n uic

Define a parameter :

.param vp = 3.0v

Calculate maximum voltage of signal Vout from 4 ns to 10 ns

.meas tran vmax max v(Vout) from 4n to 10n

Calculate minimum voltage of signal Vout from 6 ns to 15 ns

.meas tran vmin min v(Vout) from 6n to 15n

Calculate the fall delay between the falling edge of the signal Vin and the falling edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_f trig v(Vin) val=’vp/2′ fall=1 targ v(Vout) val=’vp/2′ fall=1

Calculate the rise delay between the rising edge of the signal Vin and the rising edge of signal Vout. (note the use of parameter ‘vp’ here)

.meas tran delay_r trig v(Vin) val=’vp/2′ rise=1 targ v(Vout) val=’vp/2′ rise=1

These are the basic .meas commands which can be extended for ripple calculation and many of the user’s needs. The above image, created with ‘dia’, describes visually those commands.

Upon simulation, ngspice will output :

Transient Analysis

vmax                =  3.300000e+00 at=  1.000000e-08

vmin                =  2.589696e-04 at=  1.480631e-08

delay_f           =  4.780022e-10 targ=  1.052800e-08 trig=  1.005000e-08

pdelay_r           =  2.980831e-10 targ=  5.448083e-09 trig=  5.150000e-09

More examples can be found about the .meas command with

$  rpm -qld ngspice-doc | grep meas

Filed under: asic, eda, feature, fedora, Free Electronic Lab, ngspice

[FEL]: Circuit simulation improved

Paolo Nenzi, Dietmar, Holger Vogt and Robert Larice have contributed to the enhanced stability with the new ngspice rework 20 release. ngspice rework 20 has already been pushed to fedora stable repositories with the following enhancements:

  • Model names can start with a number like 1N4001
  • .global command reinstated (was disabled)
  • Error messages now display line number of input deck
  • [feature]: .measure with tran, ac and dc (not yet complete, e.g DERIV is missing)
  • [feature]: sysinfo command added
  • [device]: Updated bsim4 model to BSIM 4.6.5
  • [device]: Added PWL functionality for B sources

Currently Holger Vogt is kindly looking after my variable instantiation feature request for the .measure command. Hopefully after some testing, we can push another release to the stable repositories so that fedora users can largely benefit from it as soon as possible. I will write another blog post to demonstrate how to use this small but valuable feature.

Al Davis, who is working behind gnucap, is considering system-c plugins for gnucap, probably without their run-time package. Gnucap provides a lot of the needed run time support already. It might be all that is needed is to map the interface. That said, we will have to update fedora gnucap package to the latest development snapshots with the help of Rakesh Pandit (current fedora gnucap maintainer). This will give fedora users the chance to use gnucap plugins and latest enhancements over the current 0.35 stable repositories. This deserves another blog post :) .

Arun Sag is working on pushing some emacs mode to the fedora repositories. Among these emacs modes, there are irsim-mode and and spice-mode (see the above screenshot). Many users will enjoy the look-and-feel on their fedora emacs. I’m taking the opportunity to remind Fedora users that irsim has stuck-at fault simulation and power estimation capabilities.

Filed under: eda, emacs, fedora, Free Electronic Lab, gnucap, ngspice

[FEL]: Icarus Verilog bug statistics

Cary R. published some statistics about the amount of time spent in bug fixing for the most widely used opensource verilog simulator, Icarus Verilog. I’m quoting:

Excluding the VHDL work, so far in 2009 we have had 25 invalid bug reports, 87 valid bug reports. Eight of these are still open. It took on average 12 days to fix a bug and the open bugs have been open for an average of 177 days. That attached plot shows the details much better.

Icarus Verilog development team is heading towards the release of 0.9.2, which will be realeased pretty soon. If you are encountering some other bugs on 0.9.1 (the current fedora iverilog version), please do file bug reports so that they can be fixed for the 0.9.2 release.

In the past, I’ve described how to use iverilog for post-synthesis simulation and how to access documentation quickly to ensure interoperability and other verilog variants. If you are encountering issues while dealing with FPGA and iverilog, please feel free to share it with us.

Filed under: eda, iverilog

[FEL]: xcircuit 3.6 series tagged as stable

Tim Edwards has tagged version 3.6 to stable, and version 3.7 is the new development version.

The stable release will only be updated with bug fixes, while all new development and experimental stuff will go into the development release.

Users will experience fast UI responses with the new stable release 3.6.163, which has just been pushed to Fedora updates. This release also unleashes extra capabilities for managing big IC projects, which was lacking in the 3.4 series.

Filed under: eda, Free Electronic Lab, xcircuit

22nd Interop Forum: 1/3 of EDA software is pirated

Karen Bartleson reports some interesting facts from the 22nd EDA Interoperability forum in her blog.

Richard Paw represented the EDA Consortium’s OS Roadmap Committee. This group produces guidelines for operating system and hardware platforms that help unify EDA tool support around common platforms. (It drives customers crazy when the tools they purchase don’t support the same platforms.) The guidelines will be updated in September 2010. Added will be SLES 11 (SuSe Linux) and Windows 7. Dropped will be SLES 10. In 6 months, the committee will review Windows XP, Vista, and the upcoming RHEL 6 (RedHat Enterprise Linux).

Dave Graubart represented the EDA Consortium’s Anti-Piracy Committee. He said it’s hard to feel the love when you’re getting ripped off. The committee estimates that 1/3 of all EDA software use worldwide is pirated or overused beyond the license agreements. Not scientific data, but troubling nevertheless for the EDA industry. It’s easy to find the stolen binaries so most of the 1/3 estimate comes from this, not misuse/overuse which is harder to find. There are potential techniques to help prevent this piracy and the committee will continue its work to solve the problem.

Filed under: eda, events

OpenMoko Hardware development on Fedora

Designing opensource hardware projects with opensource EDA software is a challenge for anyone, well not any-more with the upcoming Fedora 12.

While assessing the risk of the project, one first needs to ensure that he/she has a robust and complete tool set before starting up with the development.

In the past, the critical path of this risk assessment was setting up the development platform, compiling and installing the whole tool set (normally composed of least 8 software) from scratch. That said, the average user should allocate one or two days just for compiling all the dependencies, after he/she has roamed around the internet in search for some possible patches needed to ensure interoperability within his/her tool set.

As the community leader in opensource EDA provider, Fedora Electronic Lab strives to eliminate this painful process by preparing this development platform beforehand and gives Fedora users the opportunity to install the required tool set within 5 minutes. During the last two months, we have been focussing on ensuring that Fedora can satisfy the needs for the electronic hardware development of the OpenMoko community.

Fedora’s Kicad will follow OpenMoko’s development needs. That said, it will require Fedora’s Kicad be pulled from trunk. Jon Ciesla, Jacek Radzikowski and I revised the entire Fedora Kicad package and spec file. It was then updated to snapshot revision 1863. But, stability of kicad will be ensured. One of the goals of FEL is not to just talk how opensource software is good, but also to support opensource hardware development and helping users to develop products out of it.

gps

We hope that the OpenMoko community can now work out of the box with

su -c “yum install kicad fped openocd psutils-perl”
svn co https://svn.openmoko.org/trunk/gta02-core/
cd gta02-core/
make update
make sch

instead of the time consuming process as described on this GETTING-STARTED document.

That said, we sincerely hope that our contribution might help OpenMoko developers seduce more contributors and reviewers easily.

Kicad’s module editor lacks automation and its output is difficult to review. Hence fped comes in as a footprint editor that captures more of the design process and allows one to annotate the footprint with measurements taken directly from the manufacturer’s datasheet.

fped

Dean Glazeski, who was privately packaging OpenOCD, (an Open On-Chip Debugger (OpenOCD) provides debugging, in-system programming and boundary-scan testing for embedded devices.) joined Fedora Project and introduced OpenOCD to Fedora so that a wider userbase can benefit from it.

OpenOCD provides a human-readable telnet interface for manually halting/resuming the target device, reading/writing registers and memory, etc. In addition, it provides a RDI (remote debugger interface) on a TCP port. This interface can be used by gdb (the GNU Debugger).

We currently have the following list of packages under the Fedora Electronic Lab umbrella for the following architectures (i686,x86_64, PPC and PPC64). If you feel that we still lack tools that are important to OpenMoko’s development, please do not hesitate to let us know.

Filed under: eda, fedora, Free Electronic Lab,

Fedora Electronic Lab 12 Release Notes

The Fedora Electronic Lab team and upstream opensource EDA developers are proud (on schedule :) ) to publish the release notes of the upcoming Fedora Electronic Lab 12 ‘Constantine’ Livedvd.

felrn

It is 26-pages long and entails in-depth information about each EDA tool which have undergone updates or introduced for this release.

Filed under: eda, fedora, Free Electronic Lab

[FEL]: Fedora vacation and Tasks before F-12′s release

As from the 14th october, I’ll be in Fedora vacation till the 25th of october. I won’t be able to answer any of your emails during that timeframe. I apologize for any inconvenience that may cause.

However, we are ahead in schedule in terms of FEL development cycle compared to Fedora-12 general release.

Since every Fedora SIG has entered final freeze and F-12 branch has already been created, I would encourage you to try rawhide or the nightly spins. I would really appreciate if you could help with the testing.

TASKS TO COMPLETE BEFORE RELEASE

FEL Spin

  • Verify that latest version (which has been built on koji) of electronics-menu, toped, fped, avra and picprog have been tagged for F-12 – TO BE DONE
  • New spin website migration ( still pending on Fedora Infrastructure progress on this )
  • Test nightly spins – TO BE DONE

Marketing materials

Opened tickets on Fedora hosted

Since these are tasks and requests for enhancements, we will have to deduce a date to migrate those tickets from FEL-12 milestone to FEL-13 milestone.

Filed under: eda, fedora, Free Electronic Lab

Profile

Chitlesh Goorah
Digital IC design engineer
Neuchâtel, Switzerland

This blog is featured on Sean Murphy's EDA blogger list.

May 2013
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