I can’t attend this EDA conference (set for July 26-31 2009 in San Francisco). So I’ll be following from Europe (on the web). The key highlights (which interest me, and possibly my inline comments as well) will be jotted down here on this page.
Tools : google reader, twitscoop
06 July 2009 – Ran Avinun blogged about Cadence’s presence at DAC
It seems to me very ESL oriented. With the recent layoffs and possible loss of interest in the digital design, what does Cadence’s Marketing want to show behind the curtains at DAC?
08 July 2009 – Andrew B Kahng (general chair of the 46th DAC) was interviewed.
- He pointed out that paper submissions were noticeably up, especially in the field of Electronic System Level and Higher Level Synthesis.
- Introduction of UserTrack during this DAC.
- Expecting 3000-3500 exhibitor participants and showing as much as possible.
08 July 2009 – Sean Murphy blogged about his interest in learning more about collaborative hardware development, a topic I have blogged earlier hoping it might be a feature for FEL-12. His blog post was a bit too Synopsys oriented.
09 July 2009 – Andrew B Kahng (general chair of the 46th DAC) exposed the FPGA section of DAC
This seems to be an attractive section for new startups. I am personally interested in these:
- Session 17: “Leveraging Parallelism in FPGAs and Multicore Systems.” This session will cover a comprehensive set of topics focusing on hardware parallelism using FPGAs and multicore computing, two timely subjects for DAC attendees.
- Session 18: “A Computing Origami: Folding Streams in FPGAs,”. The paper will describe the concept of “folding” streams onto FPGA coprocessors to create efficient design implementations.
10 July 2009 – Frank Schirrmeister will talk (at the Synopsys booth) about how software driven verification improves your overall productivity, shaving months off your product schedules.
11 July 2009 – Si2 released the schedules of their 3 Workshops.
I will follow this one: Low-Power Coalition Workshop: Advances in Low-Power Design Throughout the Design Flow.
17 July 2009 – DFT/Test sessions
John Ford blogged about the “Targeted Test and Diagnosis,” session which will address the importance of targeting the right faults with the appropriate test method. Four papers will explore advances in improved targeting methods for a range of test topics, such as
- digital test generator,
- IC diagnosis,
- embedded DRAM BIST and
- RF testing.
20 July 2009 – Cadence announced they will do a demonstration on Architectural Prototyping.
It is a way to see the economic impact of P&R decisions and optimizations, as you progress toward goals set at the architectural phase. This demo will show the integration of two powerful technologies from Cadence: Encounter Digital Implementation System and InCyte Chip Estimator to do just that. It will highlight how you can measure the current cost implications of the actual physical implementation you’re working with-and compare it to the original plan at any step in the flow.
July 20, 2009 – Jasper Design Automation and STMicroelectronics will present “Accelerating Design Reuse with Formal Technology” at next week’s DAC.