Floorplanning with Magic, how hard can that be ?

Alliance VLSI development cycle has stalled and there are many software compatibility issues that need to be solved before getting a proper (one that can meet the industry’s needs) digital backend flow with opensource software. Herb which was meant as a clone for Alliance VLSI will not be stable enough at the end of this year, nor I would expect some Mixed-Signal designs from it.

Since it won’t be TCL based, I doubt I would even use Herb myself. Hence, I’m investigating further on what should be done before one can design a mixed signal chip with the industry’s requirements.

Magic VLSI is fairly analog oriented, it is TCL based and it is lambda based. Since it is TCL based, it deserves credits. But being lambda based it makes it hard to go beyond 90nm process node with it since it won’t be accurate enough. Surely a timing correlation would prove this.

Magic’s 2 grid cells normally represent the length of the transistor. However, macro models of SRAM/ROM available in the LEF format include decimal points to reflect the position of different metal layers and vias. This is a major drawback with Magic VLSI.

Achieving digital implementation with Magic would certainly require new techniques about  how to use magic itself and how metrics (resistances, capacitances, switching activities,..) are extracted.

I started today with a case scenario: try to get a simple floorplan setup with some macro models. Nigel Nordsworth has kindly forwarded some Macro models. He is FEL’s test contributor for more than a year now. As mentioned above, LEF files might include X and Y positions with 3 decimal points in microns. Hence, to load the macro models, these X and Y positions should be multiplied by 1000 and thereby converting them into the nanometer scale.

Our current possible solution would be to use a Magic’s grid cell to represent 1 nm². This is not how one would normally use Magic. The complexity slope rises as all the tech files should be revisited and possibly be project dependent. Being project dependent, the solution would not be useful for the normal user. But once we can get a proper TCL package with can help us rotate the macro models and one of the 3 internal routers of magic can actually do some power routings (VDD and GND), we will present our solution for standardization.

instance_name ""
foreach instance [ cellname list instances ] {
    if { $instance == $element_name } {
         set instance_name $element_name
    }
}

select cell $instance_name
instance celldef $instance_name

regsub {\.} $xl {} xl
regsub {\.} $yl {} yl
move to $xl $yl

puts "Info: Moved the following selected Macro to ($xl,$yl)"

Using the above TCL commands just to move around the macro model I believe that a digital implementation should be feasible with Magic VLSI. But some intelligent mechanisms should be investigated about the timing and power correlations. As I wrote in the past, coupled with IRSIM we can even estimate leakage power out of the design during standby mode.

It should be exciting to design low power and low voltage designs.

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Filed under: alliance, asic, magic