Verilator has verilog lint capabilities aside its main robust functionality : Verilog code to C++/SystemC conversion.
# yum install verilator
$ verilator –lint-only mydesign.v
Coupled with verilog-mode, it can really boost productivity for the experienced designer just by adding the following to the .emacs file.
(setq verilog-linter “verilator –lint-only”)
Currently we are making a request to upstream so that vhdl-mode and verilog-mode bundled with emacs can be updated. Possibly this should be also be enabled by default.