Free Electronic Lab

Opensource EDA software development, some thoughts about the EDA/Semiconductor industry and Mixed-signal integrated circuit design

[FEL]: Power Estimation at transistor Level


One of the least advertised features of IRSIM is its ability to quickly estimate power of large VLSI circuits from gate level netlists (.sim).

To install IRSIM on Fedora (default on Fedora Electronic Lab):

# yum install irsim

This estimation is based on the

  • ‘three-level quantization scheme’, where the voltage can assume 3 values (GND, VDD/2 and VDD). It is fairly more accurate than the ‘two-level rail-to-rail model’.
  • measurement of glitching power.
  • estimates reasonably close to those that can be derived by measuring currents with a SPICE simulator with an error of less than 20% and a speed up of about 500 times.
  • incremental power measurement.
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Filed under: asic, opencircuitdesign

One Response

  1. [...] about the timing and power correlations. As I wrote in the past, coupled with IRSIM we can even estimate leakage power out of the design during standby [...]

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Chitlesh Goorah
Digital IC design engineer
Neuchâtel, Switzerland

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This blog is featured on Sean Murphy's EDA blogger list.

Also, on a side track, I sometimes write about the success stories of opensource EDA tools on [open electrons] on edacafe.com.

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