The title of this blog post was copied from Harry Gries’s blog post An ASIC Guy Visits An FPGA World and reflects my thoughts as a junior.
Harry’s observations are oriented towards the “raw” design methodology proposed by the FPGA design tools vendors. Coming from the ASIC environment, we are heavily design methodology oriented and work hard to satisfy design tools. But in the FPGA environment, the design tools provide an even more automated work flow from frontend to backend. Physical design sometimes (depending on the size of the design) seems to take a few minutes. I have seen people even skip the entire the physical design, unless there is a violation somewhere.
I had a few FPGA projects to handoff and though they were for some different medium-sized companies, sometimes I felt that project managers and reviewers were not serious enough like in ASIC environment. I got a few remarks for my VHDL designs which sometimes coming from a senior FPGA designer shocked me. It is true as well that FPGA design was not their prime development base.
One of those remarks which till now I have not really understood the reason between it and why my reasoning was not valid. It concerned my FSMs. They had “next-state” decoding and “output” decoding into two separate VHDL processes. My reasoning which Altera’s appplication notes implies will restrict the synthesis tool from sharing resources with other blocks. The remark I got, during a code review, was “I never seen that in my 12 years career, clean this”. I am still eager to know what advantage will my design have while combining these two processes.
I also got the most chaotic code review experience with other FPGA designers. VHDL code review was left incomplete from my point of view and discarded parts of code review with respect to switching rates, power, … due to lack of time. I was expecting a thorough code review for an optimal the sign-off and hand-off like I used to see with ASIC design teams.
I’m sure this is not true in every FPGA design team. What I was to say here is that during the excursion to the FPGA world, the strict discipline routine one has in ASIC environment just fades away. How quickly? I think it depends on the FPGA design team. I could even feel how disconnected the small companies are from the EDA vendors. However, I wish to get myself involved with a “real” high-performance FPGA based design team to see how discipline they are 
While these are issues I personally encountered, I am trying to get Fedora Electronic Lab enough collaborative solutions so that small companies can at least have a decent code review, project hand-off and make FPGA designers happy.
Chitlesh Goorah
[...] I also participated in their poll. One of the questions on the poll was about which vendor’s FPGA I am using. I am always impressed to see in such poll that 2/3 of the participants choose Xilinx’s FPGA over Altera’s FPGA. I have not yet understood the reason behind it. One of the reasons I would choose Altera’s FPGA is because their constraints are in the SDC format, whereas Xilinx uses its own. It reassures me about the certainty of the constraints I want to apply. Hence,this ensures a quicker prototyping for a junior ASIC guy like me who visits the FPGA world. [...]